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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F745VG датащи(PDF) 161 Page - STMicroelectronics |
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STM32F745VG датащи(HTML) 161 Page - STMicroelectronics |
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161 / 227 page  DocID027590 Rev 4 161/227 STM32F745xx STM32F746xx Electrical characteristics 195 SAI characteristics Unless otherwise specified, the parameters given in Table 78 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 78. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCKL SAI Main clock output - 256 x 8K 256xFs(2) MHz FSCK SAI clock frequency Master data: 32 bits - 128xFs MHz Slave data: 32 bits - 128xFs DSCK SAI clock frequency duty cycle Slave receiver 30 70 % tv(FS) FS valid time Master mode 8 22 ns tsu(FS) FS setup time Slave mode 2 - th(FS) FS hold time Master mode 8 - Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 5 - tsu(SD_SR) Slave receiver 3 - th(SD_MR) Data input hold time Master receiver 0 - th(SD_SR) Slave receiver 6 - tv(SD_ST) th(SD_ST) Data output valid time Slave transmitter (after enable edge) -15 tv(SD_MT) Master transmitter (after enable edge) -20 th(SD_MT) Data output hold time Master transmitter (after enable edge) 7- 1. Guaranteed by characterization results. 2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency) |
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