STM32F469AE datasheet(37/217 Pages) STMICROELECTRONICS

номер детали	STM32F469AE

подробное описание детали	ARMCortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/3844KB RAM, USB OTG HS/FS, Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI

PDF	217 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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DocID028196 Rev 3

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STM32F469xx

Functional overview

VBAT operation is activated when VDD is not present.

The VBAT pin supplies the RTC, the backup registers and the backup SRAM.

Note:

When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events

do not exit it from VBAT operation.

When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no

more available and VBAT pin should be connected to VDD.

2.24

Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic

timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 6 compares the features of the advanced-control, general-purpose and basic timers.

Table 6. Timer feature comparison

Timer

type

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Complementary

output

Max

interface

clock

(MHz)

Max

timer

clock

(MHz)(1)

Advanced

control

TIM1,

TIM8

16-bit

Up,

Down,

Up/down

Any integer

between 1

and 65536

Yes

180

General

purpose

TIM2,

TIM5

32-bit

Up,

Down,

Up/down

Any integer

between 1

and 65536

Yes

90/180

TIM3,

TIM4

16-bit

Up,

Down,

Up/down

Any integer

between 1

and 65536

Yes

90/180

TIM9

16-bit

Any integer

between 1

and 65536

180

TIM10

TIM11

16-bit

Any integer

between 1

and 65536

180

TIM12

16-bit

Any integer

between 1

and 65536

90/180

TIM13

TIM14

16-bit

Any integer

between 1

and 65536

90/180

Basic

TIM6,

TIM7

16-bit

Any integer

between 1

and 65536

Yes

90/180

1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the

RCC_DCKCFGR register.

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