STM32F303VD datasheet(23/173 Pages) STMICROELECTRONICS

23 / 173 page

DocID026415 Rev 5

23/173

STM32F303xD STM32F303xE

Functional overview

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

3.13

Interrupts and events

3.13.1

Nested vectored interrupt controller (NVIC)

The STM32F303xD/E devices embed a nested vectored interrupt controller (NVIC) able to

handle up to 73 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Closely coupled NVIC core interface

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.14

Fast analog-to-digital converter (ADC)

Four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6

bit, are embedded in the STM32F303xD/E family devices. The ADCs have up to 40 external

channels. Some of the external channels are shared between ADC1&2 and between

ADC3&4. The ADCs can perform conversions in single-shot or scan modes. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

The ADCs have also internal channels: Temperature sensor connected to ADC1 channel

16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 4

ADCs channel 18, VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2

connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and

VREFOPAMP4 connected to ADC4 channel 17.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

•

Interleaved sample and hold

•

Single-shunt phase current reading techniques.

The ADC can be served by the DMA controller.

Three analog watchdogs are available per ADC.

The analog watchdog feature allows very precise monitoring of the converted voltage of

one, some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

STM32F303VD датащи(PDF) 23 Page - STMicroelectronics

STM32F303VD датащи(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL