STM32F318C8 datasheet(101/125 Pages) STMICROELECTRONICS

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STM32F318C8 STM32F318K8

Electrical characteristics

107

6.3.19

DAC electrical specifications

Table 64. DAC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Analog supply voltage

DAC output buffer ON

2.4

3.6

RLOAD(1)

Resistive load

DAC output buffer ON



RO(1)

Output impedance

DAC output buffer ON



CLOAD(1)

Capacitive load

DAC output buffer ON

VDAC_OUT (1)

Voltage on DAC_OUT

output

Corresponds to 12-bit input

code (0x0E0) to (0xF1C) at

VDDA = 3.6 V 

and (0x155) and (0xEAB) at

VDDA = 2.4 V DAC output

buffer ON.

0.2

VDDA – 0.2

DAC output buffer OFF

0.5

VDDA - 1LSB

IDDA(3)

DAC DC current

consumption in quiescent

mode(2)

With no load, middle code

(0x800) on the input.

380

µA

With no load, worst code

(0xF1C) on the input.

480

µA

DNL(3)

Differential non linearity

Difference between two

consecutive code-1LSB)

Given for a 10-bit input code

±0.5

LSB

Given for a 12-bit input code

±2

LSB

INL(3)

Integral non linearity

(difference between

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 4095)

Given for a 10-bit input code

±1

LSB

Given for a 12-bit input code

±4

LSB

Offset(3)

Offset error (difference

between measured value at

Code (0x800) and the ideal

value = VDDA/2)

±10

Given for a 10-bit input code

at VDDA = 3.6 V

±3

LSB

Given for a 12-bit input code

at VDDA = 3.6 V

±12

LSB

Gain error(3) Gain error

Given for a 12-bit input code

±0.5

tSETTLING(3)

Settling time (full scale: for a

12-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±1LSB

CLOAD  50 pF,

RLOAD  5 k

-3

µs

Update rate(3)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

CLOAD  50 pF,

RLOAD  5 k

MS/s

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