XC910607 datasheet(4/7 Pages) TOREX

4 / 7 page

Preliminary

Electrical Characteristics

XC9106D003MR, XC9107D003MR

(FOSC=300 (kHz)

Ta=25OC

Test Conditions: Unless otherwise stated, CL: ceramic, recommended MOS FET should be connected.

VDD =

(V)

Vref =

(V) ,

RFB1, 2 x 10

VIN =

(V)

IOUT =

(mA)

Notes

Standard Circuit

Externally Applied Reference Voltage (Vref)

PARAMETER

SYMBOL

XC9106 / 07 Series

PWM Control, PWM/PFM Switching Control,

Step-up DC/DC Converters

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Circuit

Output Voltage

VOUT

Vref = 0.9V

8.820

9.000

9.180

Reference Voltage Range

Vref

0.8

2.5

FB Control Voltage

VFB

Vref = 0.9V

0.882

0.900

0.918

Power Supply Voltage Range

VDD

VDD as shown right or (Vref applied voltage + 0.7V)

1.8

10.0

Operation Start Voltage

VST1

Recommended Circuit using 2SD1628, IOUT=1.0mA

0.9

Oscillation Start Voltage

VST2

No external connections

CE/Vref=0.9V, Voltage applied, FB=0V

0.8

Operation Holding Voltage

VHLD

Recommended Circuit using 2SD1628, IOUT=1.0mA

0.7

Supply Current 1

IDD1

Same as VST2, VDD=3.300V

µA

Supply Current 2

IDD2

Same as IDD1, FB=1.2V

µA

Stand-by Current

ISTB

Same as IDD1, CE/Vref=0V

1.0

µA

Oscillation Frequency

FOSC

Same as IDD1

255

300

345

KHz

Maximum Duty Ratio

MAXDTY Same as IDD1

PFM Duty Ratio

PFMDTY No Load

(XC9106 series)

Efficiency

EFFI

Recommended Circuit using XP161A1355

Soft-start Time

TSS

Vref=0.9V

5.0

10.0

20.0

CE "High" Voltage

VCEH

Same as IDD1

0.65

CE "Low" Voltage

VCEL

Same as IDD1

0.20

EXT "High" ON Resistance

REXTH

Same as IDD1, VEXT=VOUT-0.4V

Ω

EXT "Low" ON Resistance

REXTL

Same as IDD1, VEXT=0.4V

Ω

CE "High" Current

ICEH

Same as IDD2, CE=2.5V

0.0

2.5

µA

CE "Low" Current

ICEL

Same as IDD2, CE=0V

-0.1

µA

FB "High" Current

IFBH

Same as IDD2, CE=VDD

0.1

µA

FB "Low" Current

IFBL

Same as IDD2, CE=0V

-0.1

µA

3.30

0.09

3.30

Although the IC starts step-up operations from a VDD of 0.8V, the output voltage and oscillation frequency are stabilized at

VDD

≥ 1.8V or (Vref applied voltage + 0.7V). Therefore, a VDD of more than 1.8V or (Vref applied voltage + 0.7V) is recommended when

VDD is supplied from VIN or other power sources.

When obtaining VDD from a source other than VOUT, please

insert a capacitor CDD between the VDD pin and the GND pin in

order to provide stabler operations.

Please wire CL & CIN between the VOUT/VDD pin and the GND

pin. Strengthen the wiring sufficiently. When using a capacitor

other than ceramic or low ESR at CL, please take away

RSENSE and short.

Insert Rb and CB when using a

bipolar NPN Transistor.

VOUT

Nch Power

MOS FET

RSENSE

VIN

RFB1

RFB2

CFB

CE/Vref

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