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WM8738ED датащи(PDF) 8 Page - Wolfson Microelectronics plc

номер детали WM8738ED
подробное описание детали  24 BIT STEREO ADC
PDF  15 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8738ED датащи(HTML) 8 Page - Wolfson Microelectronics plc

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WM8738
Production Data
w
PD Rev 4.3 November 2004
8
DIGITAL AUDIO INTERFACE TIMING
M CLK
t
MCLKH
t
MCLKY
t
MCLKL
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
TMCLKH
10
ns
MCLK System clock pulse width low
TMCLKL
10
ns
MCLK System clock cycle time
TMCLKY
27
ns
BCLK
LRCLK
t
BCH
t
BCL
t
BCY
SDATO
t
LRS U
t
LRH
t
DD
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
80
ns
BCLK pulse width high
tBCH
40
ns
BCLK pulse width low
tBCL
40
ns
LRCLK set-up time to BCLK
rising edge
tLRSU
10
ns
LRCLK hold time from
BCLK rising edge
tLRH
10
ns
SDATO propagation delay
from BCLK falling edge
tDD
10
ns



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