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LPS22HB датащи(PDF) 12 Page - STMicroelectronics |
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LPS22HB датащи(HTML) 12 Page - STMicroelectronics |
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12 / 49 page ![]() Mechanical and electrical specifications LPS22HB 12/49 DocID027083 Rev 5 3.3 Communication interface characteristics 3.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and TOP. Figure 4. SPI slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 6. SPI slave timing values Symbol Parameter Value(1) 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. Unit Min Max tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10 MHz tsu(CS) CS setup time 6 ns th(CS) CS hold time 8 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 50 th(SO) SDO output hold time 9 tdis(SO) SDO output disable time 50 |
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