MICRF506BML datasheet(23/28 Pages) MICREL

23 / 28 page

Micrel

MICRF506

September 2004

M9999-092904

(408) 955-1690

When Modulation1 Modulation0 is 10, two sets of

divider values need to be programmed. The formula

for calculating the M, N and A values is given in

chapter Frequency synthesizer. The divider values

stored in the M0-, N0-, and A0- registers will be used

when transmitting a ‘0’ and the M1-, N1-, and A1-

registers will be used to transmit a ‘1’. The difference

between the two carrier frequencies corresponds to

the double sided frequency modulation. Opposite

from the modulation with the modulator, the PLL

shall now lock on a new frequency for every change

in the transmitted data. The PLL bandwidth therefore

needs to be relatively high, higher bit rate requires a

higher PLL bandwidth and vice versa. The data to

be transmitted shall be applied to pin DataIXO (see

chapter Transceiver sync-/non-synchronous mode

on how to use the pin DataClk). The DataIXO pin is

set as input in transmit mode and output in receive

mode. When set as input, a weak voltage divider will

set the level to Vdd/2, when it is not pulled up or

down by the controller. When using the modulator, it

is important that the DataIXO is kept tristated until

the transmission shall begin (when PLL is in lock

and the PA is turned on). When Data IXO is

tristated, the PLL will lock on the LO frequency

(used in receive mode). When DataIXO is set either

high or low, the RF frequency will be shifted up or

down, centered around the LO-frequency. This is

only important when using the modulator, for the

other modulation method, if DataIXO is tristated, the

M0-, N0- and A0-registers will be used.

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