TSB81BA3 datasheet(13/57 Pages) TI

13 / 57 page

TSB81BA3, TSB81BA3I

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

(continued)

thermal characteristics

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

RθJA

Junction-to-free-air thermal resistance

Board mounted, No air flow, High conductivity TI

recommended test board, chip soldered or greased to

19.04

°C/W

RθJC Junction-to-case-thermal resistance

recommended test board, chip soldered or greased to

thermal land with 2 oz. copper

0.17

°C/W

RθJA

Junction-to-free-air thermal resistance

Board mounted, No air flow, High conductivity TI

recommended test board with thermal land but no solder

31.52

°C/W

RθJC Junction-to-case-thermal resistance

recommended test board with thermal land but no solder

or grease thermal connection to thermal land with 2 oz.

copper

0.17

°C/W

RθJA

Junction-to-free-air thermal resistance

Board mounted, No air flow, High conductivity JEDEC

49.17

°C/W

RθJC Junction-to-case-thermal resistance

Board mounted, No air flow, High conductivity JEDEC

test board with 1 oz. copper

3.11

°C/W

switching characteristics

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

TP differential rise time, transmit

10% to 90%,

At 1394 connector

0.5

1.2

TP differential fall time, transmit

90% to 10%,

At 1394 connector

0.5

1.2

tsu

Setup time, CTL0, CTL1, D1−D7, LREQ to

PCLK

1394a−2000

50% to 50%,

See Figure 2

2.5

Hold time, CTL0, CTL1, D1−D7, LREQ

after PCLK

1394a−2000

50% to 50%,

See Figure 2

tsu

Setup time, CTL0, CTL1, D1−D7, LREQ to

LCLK

1394b

50% to 50%,

See Figure 2

2.5

Hold time, CTL0, CTL1, D1−D7, LREQ

after LCLK

1394b

50% to 50%,

See Figure 2

Delay time, PCLK to CTL0, CTL1, D1−D7,

PINT

1394a−2000

and 1394b

50% to 50%,

See Figure 3

0.5

PARAMETER MEASUREMENT INFORMATION

TPAx+

TPBx+

TPAx−

TPBx−

Ω

Figure 1. Test Load Diagram

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