PIC18F1220 datasheet(59/310 Pages) MICROCHIP

59 / 310 page

 2004 Microchip Technology Inc.

DS39605C-page 57

PIC18F1220/1320

6.0

FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A “Bulk Erase” operation

may not be issued from user code.

While writing or erasing program memory, instruction

fetches cease until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP

6.1

Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data

RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program

memory and place it into TABLAT in the data RAM

space. Figure 6-1 shows the operation of a table read

with program memory and data RAM.

Table write operations store data from TABLAT in the

data memory space into holding registers in program

memory. The procedure to write the contents of the

holding registers into program memory is detailed in

Section 6.5 “Writing to Flash Program Memory”.

Figure 6-2 shows the operation of a table write with

program memory and data RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block

can start and end at any byte address. If a table write is

being used to write executable code into program

memory, program instructions will need to be word

aligned (TBLPTRL<0> = 0).

The EEPROM on-chip timer controls the write and

erase times. The write and erase voltages are gener-

ated by an on-chip charge pump rated to operate over

the voltage range of the device for byte or word

operations.

FIGURE 6-1:

TABLE READ OPERATION

Table Pointer(1)

Table Latch (8-bit)

Program Memory

TBLPTRH

TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note

1: Table Pointer points to a byte in program memory.

Program Memory

(TBLPTR)

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