PCA9517DP datasheet(4/13 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

PCA9517

Level translating I2C-bus repeater

2004 Oct 05

APPLICATION INFORMATION

A typical application is shown in Figure 3. In this example, the

system master is running on a 3.3 V I2C-bus while the slave is

connected to a 1.2 V bus. Both buses run at 400 kHz. Master

devices can be placed on either bus.

The PCA9517 is 5 V tolerant so it does not require any additional

circuitry to translate between 0.9 V to 5.5 V bus voltages and

2.7 V to 5.5 V bus voltages.

SW02166

BUS B

BUS

MASTER

400 kHz

SLAVE

400 kHz

PCA9517

SDA

SDAB

SDA

SCL

SCLB

SCL

BUS A

3.3 V

1.2 V

SDAA

SCLA

VCCA

VCCB

10 k

Ω

10 k

Ω

10 k

Ω

10 k

Ω

Figure 3. Typical application

When the A side of the PCA9517 is pulled LOW by a driver on the

I2C-bus, a comparator detects the falling edge when it goes below

0.3VCCA and causes the internal driver on the B side to turn on,

causing the B side to pull down to about 0.5 V. When the B side of

the PCA9517 falls, first a CMOS hysteresis type input detects the

falling edge and causes the internal driver on the A side to turn on

and pull the A side pin down to ground. In order to illustrate what

would be seen in a typical application, refer to Figures 6 and 7. If the

bus master in Figure 3 were to write to the slave through the

PCA9517, waveforms shown in Figure 6 would be observed on the

A bus. This looks like a normal I2C transmission except that the

HIGH level may be as low as 0.9 V, and the turn on and turn off of

the acknowledge signals are slightly delayed.

On the B bus side of the PCA9517, the clock and data lines would

have a positive offset from ground equal to the VOL of the PCA9517.

After the 8th clock pulse, the data line will be pulled to the VOL of the

slave device which is very close to ground in this example. At the

end of the acknowledge, the level rises only to the LOW level set by

the driver in the PCA9517 for a short delay while the A bus side

rises above 0.3VCCA then it continues HIGH. It is important to note

that any arbitration or clock stretching events require that the LOW

level on the B bus side at the input of the PCA9517 (VIL) be at or

below 0.4 V to be recognized by the PCA9517 and then transmitted

to the A bus side.

SW02347

BUS

MASTER

SLAVE

400 kHz

PCA9517

SDA

SDAA

SDA

SCL

SCLA

SCL

VCCA

VCCB

SDAB

SCLB

10 k

Ω

10 k

Ω

10 k

Ω

10 k

Ω

SLAVE

400 kHz

PCA9517

SDAA

SDA

SCLA

SCL

SDAB

SCLB

10 k

Ω

10 k

Ω

SLAVE

400 kHz

PCA9517

SDAA

SDA

SCLA

SCL

SDAB

SCLB

10 k

Ω

10 k

Ω

Figure 4. Typical star application

Multiple PCA9517 A sides can be connected in a star configuration, allowing all nodes to communicate with each other.

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