10

PRELIMINARY

AT91SAM7A1 Summary

6048AS–ATARM–07/04

Special Function

Module (SFM)

The AT91SAM7A1 provides registers which implement the following special functions:

•

Chip identification

•

RESET status

Analog-to-digital

Converter (ADC)

The 8-channel, 10-bit Analog-to-Digital Converter (ADC) is based on a Successive

Approximation Register (SAR) approach. The ADC has eight analog input pins,

ANA0IN0 to ANA0IN7, and provides an interrupt signal to the AIC. The ADC has two

dedicated analog power supply pins, VDDANA and GND, and the input reference volt-

age pin, VREFP. Each channel can be enabled or disabled independently, and has its

own data register. The ADC can be configured to automatically enter Sleep Mode after a

conversion sequence, and can be triggered by the software. The ADC allows a data

transfer with the PDC.

Power Management

Controller (PMC)

The AT91SAM7A1 Power Management Controller allows optimization of power con-

sumption. The PMC enables/disables the clock inputs of PDC and ARM core. Moreover,

the main oscillator, the PLL and the analog peripherals can be put in standby mode,

allowing minimum power consumption to be obtained. The PMC provides the following

operating modes:

•

Normal: Clock generator provides clock to chip

•

Wait mode: ARM core clock is deactivated

•

Slow mode: clock generator is deactivated, the system is clocked at 32.768 kHz

Each peripheral clock can be independently stopped or started directly in the peripheral

to further reduce power consumption in Normal, Wait and Slow Modes.

ICE Debug Mode

ARM Standard Embedded In Circuit Emulation is supported via the ICE port. It is con-

nected to a host computer via an external ICE Interface. In ICE Debug Mode, the ARM

core responds with a non-JTAG chip ID which identifies the core to the ICE system. This

is not JTAG IEEE 1149.1 compliant.