AX8052F151 datasheet(21/34 Pages) ONSEMI

21 / 34 page

AX8052F151

www.onsemi.com

The AX8052F151 also features two analog comparators.

Each comparator can either compare two voltages on

dedicated PA pins, or one voltage against the internal 1 V

reference. The comparator output can be routed to a

dedicated digital output pin or can be read by software. The

comparators are clocked with the system clock.

Figure 7. ADC Block Diagram

Temperature

Sensor

ADC Core

Clock

Trigger

Gain

Ref

VREF

1 V

VDDIO

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PPP

NNN

One Shot

Free Running

Timer 0

Timer 1

Timer 2

PC4

ADC Result

ACOMP1REF

ACOMP1ST/PA7/PC1

ACOMP1IN

ACOMP1INV

ACOMP0IN

ACOMP0REF

ACOMP0INV

ACOMP0ST/PA4/PC3

System Clock

ADCCONV

Single Ended

0.5 V

DMA Controller

The AX8052F151 features a dual channel DMA engine.

Each DMA channel can either transfer data from XRAM to

almost any peripheral on chip, or from almost any peripheral

to XRAM. Both channels may also be cross−linked for

memory−memory transfers. The DMA channels use buffer

descriptors to find the buffers where data is to be retrieved

or placed, thus enabling very flexible buffering strategies.

The DMA channels access XRAM in a cycle steal fashion.

They access XRAM whenever XRAM is not used by the

microcontroller. Their priority is lower than the

microcontroller, thus interfering very little with the

microcontroller. Additional logic prevents starvation of the

DMA controller.

AX8052F151 датащи(PDF) 21 Page - ON Semiconductor

AX8052F151 датащи(HTML) 21 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL