2-OUTPUT 3.3V PCIE CLOCK GENERATOR

8

OCTOBER 18, 2016

9FGL02 DATASHEET

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked

(CC) Architectures

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate

Electrical Characteristics–DIF LP-HCSL Output Unfiltered Phase Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Notes

PCIe Gen 1

20

25

86

ps

(p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

0.5

0.6

3

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

1.3

1.6

3.1

ps

(rms)

1,2

PCIe Gen 3

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.36

0.50

1

ps

(rms)

1,2

PCIe Gen 4

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.36

0.50

0.5

ps

(rms)

1,2

Phase Jitter

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Notes

SRIS

PCIe Gen 2

(PLL BW of 16MHz , CDR = 5MHz)

0.7

1.1

2

ps

(rms)

1,2

SRIS

PCIe Gen 3

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

0.5

0.65

0.7

ps

(rms)

1,2

Phase Jitter, PLL Mode

specifications. There is a proposal to reduce the PCIe Gen3 limit to 0.5ps.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Phase Jitter, 12k-20M

100MHz outputs with REF output enabled

SSC Off

1.5

2

N/A

ps

(rms)