8P34S2108NLGI datasheet(11/20 Pages) IDT

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October 20, 2016

8P34S2108 Datasheet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 3 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage

swing. For example, if the input clock swing is 1.8V and VDD = 1.8V, R1 and R2 value should be adjusted to set V1 at 0.9V. The values

below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50

 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading

for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while

maintaining an edge rate faster than 1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential

signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD

+ 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized

for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.

Figure 3. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

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