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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72774 датащи(PDF) 18 Page - STMicroelectronics |
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ST72774 датащи(HTML) 18 Page - STMicroelectronics |
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18 / 144 page  ST72774/ST727754/ST72734 18/144 3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a crystal or an external clock signal to drive the internal oscillator. The internal clock (CPU CLK running at fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3. Depending on the external quartz or clock frequency, a division factor of 2 is optionally added to generate the 12 MHz clock for the Sync Processor (clamp function) as shown in Figure 7 and a second divider by 2 for the 6MHz USB clock. The CPU clock is used also as clock for the ST727x4 peripherals. Note: In the Sync processor, an additional divider by two is added in fast mode (same external timing for this peripheral). Figure 7. Clock divider chain %3 12 MHz (Sync processor Clampout signal) fCPU: 4 or 8 MHz (CPU and peripherals) OSC 12 MHz %2 FAST or 24MHz FAST=1 for 24MHZ oscillator FAST=0 for 12 MHz oscillator %2 6 MHz (USB) 12 MHz or 24MHz (TMU) 4 |
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