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EP7312 датащи(PDF) 39 Page - Cirrus Logic

номер детали EP7312
подробное описание детали  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
PDF  54 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

EP7312 датащи(HTML) 39 Page - Cirrus Logic

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©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
39
EP7311
High-Performance, Low-Power System on Chip
V2
VSSIO
Pad ground
I/O ground
V3
VSSIO
Pad ground
I/O ground
V4
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D /
SDRAM byte lane
mask
V5
PD[4]
1
Low
I/O
GPIO port D
V6
PD[2]
1
Low
I/O
GPIO port D
V7
SSICLK
1
Input
‡
I/O
DAI/CODEC/SSI2
serial clock
V8
SSIRXDA
I/O
DAI/CODEC/SSI2
serial data input
V9
nADCCS
1
High
O
SSI1 ADC chip
select
V10
VDDIO
Pad power
Digital I/O power,
3.3V
V11
ADCCLK
1
Low
O
SSI1 ADC serial
clock
V12
COL[7]
1
High
O
Keyboard scanner
column drive
V13
COL[4]
1
High
O
Keyboard scanner
column drive
V14
TCLK
IJTAG clock
V15
BUZ
1
Low
O
Buzzer drive output
V16
D[29]
1
Low
I/O
Data I/O
V17
A[26]/DRA[1]
2
Low
O
System byte address
/ SDRAM address
V18
VDDIO
Pad power
Digital I/O power,
3.3 V
V19
VDDIO
Pad power
Digital I/O power,
3.3 V
V20
A[24]/DRA[3]
‘
Low
O
System byte address
/ SDRAM address
W1
VSSIO
Pad ground
I/O ground
W2
VSSIO
Pad ground
I/O ground
W3
VSSIO
Pad ground
I/O ground
W4
PD[6]/SDQM[0]
1
Low
I/O
GPIO port D /
SDRAM byte lane
mask
W5
TMS
with p/u*
I
JTAG mode select
W6
PD[1]
1
Low
I/O
GPIO port D
W7
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2
frame sync
W8
SSIRXFR
1
Input
‡
I/O
DAI/CODEC/SSI2
frame sync
W9
VSSCORE
Core Ground
Core Ground
W10
DRIVE[1]
2
High /
Low
I/O
PWM drive output
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
Strength
†
Reset
State
Type
Description



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