DM9000 datasheet(9/54 Pages) ETC

9 / 54 page

DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

Version: DM9000-DS-F02

June 26, 2002

EECK

Clock to EEPROM

EECS

I/O

Chip Select to EEPROM

This pin is also used as a strap pin to define the LED modes.

When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0

Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally

5.4 Clock Interface

X2_25M

Crystal 25MHz Out

X1_25M

Crystal 25MHz In

CLK20MO

20Mhz Clock Output

It is used as the clock signal for the external MII device’s clock is 20MHz

This pin has a pulled down resistor about 60k ohm internally.

5.5 LED

Interface

SPEED100#

Speed LED

Its low output indicates that the internal PHY is operated in 100M/S, or it

is floating for the 10M mode of the internal PHY

DUP#

Full-duplex LED

In LED mode 1, Its low output indicates that the internal PHY is operated

in full-duplex mode, or it is floating for the half-duplex mode of the internal

PHY

In LED mode 0, Its low output indicates that the internal PHY is operated

in 10M mode, or it is floating for the 100M mode of the internal PHY

LINK&ACT#

Link LED

In LED mode 1, it is the combined LED of link and carrier sense signal of

the internal PHY

In LED mode 0, it is the LED of the carrier sense signal of the internal

PHY only

5.6 10/100 PHY/Fiber

Fiber-optic Signal Detect

PECL signal, which indicates whether or not the fiber-optic receive pair is

receiving valid levels

BGGND

Bandgap Ground

BGRES

I/O

Bandgap Pin

AVDD

Bandgap and Guard Ring Power

AVDD

RX Power

RXI+

TP RX Input

RXI-

TP RX Input

AGND

RX Ground

AGND

TX Ground

TXO+

TP TX Output

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