ADN8810

Rev. 0 | Page 13 of 16

DITHER

4.096V

R1

1.62k

Ω

R2

1.62k

Ω

C

1

µF

5V

AD8605

Figure 19. Adding Dither to the Reference Voltage

Set the gain of the dither by adjusting the ratio of R2 to R1.

Increase C to lower the cutoff frequency of the high-pass filter

created by C and R1. The cutoff frequency of Figure 19 is

approximately 10 Hz.

The AD8605 is recommended as a low offset, rail-to-rail input

amplifier for this circuit.

DRIVING COMMON-ANODE LASER DIODES

The ADN8810 can power common-anode laser diodes. These

are laser diodes whose anodes are fixed to the laser module

case. The module case is typically tied to either VDD or ground.

For common-anode-to-ground applications, a negative 5 V

supply must be provided.

4096

5

.

16

1

1

1

.

1

096

.

4

Code

k

R

I

S

×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+

×

=

(5)

where Code is an integer value from 0 to 4,095. Using the values

in Figure 20, the diode current is 300.7 mA at a code value of

2,045 (0x7FF), or one-half full-scale. This effectively provides

11-bit current control from 0 mA to 300 mA of diode current.

The maximum output current of this configuration is limited by

the compliance voltage at the IOUT pin of the ADN8810. The

voltage at IOUT cannot exceed 1 V below PVDD, in this case

the gate-to-source voltage of the external FET. For this reason,

select a FET with a low threshold voltage.

voltage at the cathode of the laser diode. Given a forward laser

of Code in Equation 5.

Although the configuration for anode-to-ground diodes is

similar, the supply voltages must be shifted down to 0 V and

–5 V, as shown in Figure. The AVDD, DVDD, and PVDD pins

are connected to ground with AVSS connected to –5 V. The

4.096 V reference must also be referred to the –5 V supply

voltage. The diode current is still determined by Equation 5.

All logic levels must be shifted down to 0 V and –5 V levels as

well. This includes RESET, CS, SCLK, SDI, SB, and all ADDR

pins. Figure shows a simple method to level shift a standard

TTL or CMOS (0 V to 5 V) signal down using external FETs.

FB

NC

D1

I = 300mA

@ CODE 0x7F

FDC633N

OR EQUIV

IOUT

3

VOUT

VIN

GND

ADR292

6.81

Ω

NOTE: LEAVE FB WITH NO CONNECTION

ADN8810

5V

DGND

DVSS

AVSS

5V

5V

SB

PVDD

AVDD

DVDD

ENCOMP

ADDR0-2

SDI

SCLK

TTL/CMOS

LOGIC LEVELS

CS

RESET

VREF

Figure 20. Driving Common-Anode-to-VDD Laser Diodes

FB

NC

D1

I = 300mA

@ CODE 0x7F

FDC633N

OR EQUIV

IOUT

3

VOUT

VIN

GND

ADR292

6.81

Ω

NOTE: LEAVE FB WITH NO CONNECTION

ADN8810

–5V

–5V

–5V

–5V

DGND

DVSS

AVSS

SB

PVDD

AVDD

DVDD

ENCOMP

ADDR0-2

SDI

SCLK

–5 TO 0V

LOGIC LEVELS

CS

RESET

VREF

Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a Negative

Supply

NDC7003P

OR EQUIV

10k

Ω

100k

Ω

TO:

+3V

–5V

–5V

TTL/CMOS

LEVEL

RESET

CS

SCLK

SDI

NDC7002N

OR EQUIV

Figure 22. Level Shifting TTL/CMOS Logic

PC BOARD LAYOUT RECOMMENDATIONS

Although they can be driven from the same power supply

voltage, keep DVDD and AVDD current paths separate on the

PC board to maintain the highest accuracy; likewise for AVSS

and DGND. Tie common potentials together at a single point

located near the power regulator. This technique is known as

star grounding and is shown in Figure. This method reduces

digital crosstalk into the laser diode or load.