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GL811USB датащи(PDF) 16 Page - List of Unclassifed Manufacturers

номер детали GL811USB
подробное описание детали  USB 2.0 to ATA / ATAPI Bridge Controller
PDF  36 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
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GL811USB датащи(HTML) 16 Page - List of Unclassifed Manufacturers

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GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
©2000-2002 Genesys Logic Inc.—All rights reserved.
Page 15
6.4.1 Register transfers
Notes:
1.Device address consists of signals CS0_, CS1_ and DA(2:0).
2.Data consists of IODD(7:0).
3.The negation of IORDY by the device is used to extend the register transfer cycle. The
determination of whether the cycle is to be extended is made by the host after tA from the
assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as
following:
t0
t1
t2
t9
t2i
t3
t4
t5
t6
t6z
tA
tC
tRD
tC
tB
ADDR valid
(Note1)
DIOR_/DIOW_
WRITE IODD(7:0)
(Note2)
Read IODD(7:0)
(Note2)
IORDY (Note3.1)
IORDY (Note3.2)
IORDY (Note3.3)



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