V370PDC

4

V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101

Copyright © 1999, V3 Semiconductor Inc.

CAS

Z

SDRAM Column Address Strobe

MWE

Z

SDRAM Memory Write Enable

MAD[31:0]

Z

SDRAM and peripheral bus data

DQM[3:0]

Z

SDRAM Data Mask (these act as MBE[3:0], A[1:0] for peripheral

access)

MARB_IN

I

Peripheral bus arbitration input: Treated as bus request input

when V370PDC is the primary bus master. When V370PDC is the

secondary bus master, this input acts as bus grant.

MARB_OUT

0

Peripheral bus arbitration output: Treated as bus grant output

when V370PDC is the primary bus master. When V370PDC is the

secondary bus master, this output acts bus request.

ALE

Z

Address Latch Enable: used to latch the address on MAD[31:0]

during the address phase of a peripheral bus access.

ADS

Z

Asserted low to indicate the beginning of a bus cycle.

BLAST

Z

Burst last.

READY

I

Data ready.

WNR

ZWrite/Read.

SDA

I/OD

Z

Serial EEPROM Data

SCL

Z

Serial EEPROM Clock

IOC[11:0]

Z

Multi-purpose I/O that can be configured for many functions

INT[3:0]

Z

General purpose interrupt inputs/outputs: may be used for either

PCI or local processor interrupts

Mode and Reset

Signal

Type

R

Description

RSTIN

I

Reset Input: Active low reset input used to initialize all internal

functions of the chip.

RSTOUT

0

Reset Output: Driven active when the input reset is driven active.

Driven inactive when the RSTOUT bit in the system register is set.

The RSTOUT signal is synchronous to the rising edge of CLKIN.

CH

I

PCI Precharge Bias: This signal is driven low to activate the on-

chip precharge bias for use in PICMG Hot Swap applications.

Non-Hot Swap applications should pull this signal high.

Table 3: Signal Descriptions (cont’d)