RT9230CS datasheet(5/10 Pages) ETC

5 / 10 page

RT9230

DS9230-03 July 2001

www.richtek-ic.com.tw

Functional Pin Description

UGATE1, UGATE2 (Pins 27 and 1)

Connect UGATE pins to the respective PWM

converter’s upper MOSFET gate. This pin provides

the gate drive for the upper MOSFETs.

PHASE1, PHASE2 (Pins 26 and 2)

Connect the PHASE pins to the PWM converter’s

upper MOSFET source. These pins are used to

monitor the voltage drop across the upper MOSFETs

for over-current protection.

VID0, VID1, VID2, VID3, VID4 (Pin 7, 6, 5, 4, and 3)

VID0-4 are TTL-compatible the input pins to the 5-bit

DAC. The state logic of these five pins program the

internal voltage reference, DACOUT. The level of

DACOUT sets the microprocessor core converter

output voltage, as well as the corresponding PGOOD

and OVP thresholds. Table 1 specifies the DACOUT

voltage of 32 combinations of VID levels.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate

the status of the PWM converter output voltage. This

pin is pulled low when the synchronous regulator

output is not within

±10% of the DACOUT reference

voltage, or when any of the other outputs are below

their under-voltage thresholds. The PGOOD output

is open for ‘11111’ VID code.

OCSET1, OCSET2 (Pins 23 and 9)

Connect a resistor (ROCSET) from this pin to the drain

of the upper MOSFET. ROCSET, an internal 200

µA

current source (IOCSET), and the upper MOSFET on-

resistance (RDS(ON)) set the converter over-current

(OC) trip point according to the following equation:

IOCSET×ROCSET

IPEAK =

RDS(ON)

An over-current trip cycles the soft-start function.

The voltage at this pin is monitored for power-on

reset (POR) purposes and pulling this pin low with an

open drain device will shutdown the IC.

VSEN2 (Pin 10)

Connect this pin to the output of the standard buck

PWM regulator. The voltage at this pin is regulated to

the level pre-determined by the logic-level status of

the SELECT pin. This pin is also monitored by the

PGOOD comparator circuit.

SELECT (Pin 11)

This pin determines the output voltage of the AGP

bus switching regulator. A low TTL input sets the

output voltage to 1.5V while a high input sets the

output voltage to 3.3V.

SS (Pin 12)

Connect a capacitor from this pin to ground. This

capacitor, along with an internal 28

µA (VSS>1V)

current source, sets the soft-start interval of the

converter.

FAULT (Pin 13)

This pin is low during normal operation, but it is

pulled to about 8V (VCC = 12V) in the event of an

over-voltage or over-current condition.

VSEN4 (Pin 14)

Connect this pin to the output of the 1.8V regulator.

This pin is monitored for under-voltage events.

DRIVE4 (Pin 15)

Connect this pin to the gate of an external MOSEFT.

This pin provides the drive for the 1.8V regulator’s

pass transistor.

VAUX (Pin 16)

The +3.3V input voltage at this pin is monitored for

power-on reset (POR) purpose. Connected to +5V

input, this pin provides boost current for the two

linear regulator output drives in the event bipolar

NPN transistors (instead of N-channel MOSFETs)

are employed as pass elements.

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