DM9008F datasheet(45/68 Pages) ETC

45 / 68 page

DM9008

ISA/Plug & Play Super Ethernet Contoller

Final

Version :DM9008-DS-F02

June 14, 2000

Alignment of the Received Packet in the FIFO

Reception of the packet in the FIFO begins at location zero.

After the FIFO pointer reaches the last location in the FIFO, the

pointer wraps to the top of the FIFO, overwriting the previously

received data. This process continues until the last byte is

received. The ENC then appends the received byte count in

the next two locations of the FIFO. The value of the next FIFO

location is 0. The number of bytes used in the loopback packet

determines the alignment of the packet in the FIFO. The

alignment for a 64-byte packet is shown below.

FIFO LOCATION

FIFO CONTENTS

LOWER BYTE COUNT

UPPER BYTE COUNT

LAST BYTE

CRC1

CRC2

CRC3

CRC4

For the following alignment in the FIFO, the packet length

should be (N x 8) + 5 bytes. Note that if the CRC bit in TCR is

set, CRC will not be appended by the transmitter. If CRC is

appended by the transmitter, the last four bytes, bytes N-3 to

N, will correspond to the CRC.

FIFO LOCATIONFIFO CONTENTS

BYTE N-4

BYTE N-3 (CRC1)

BYTE N-3 (CRC2)

BYTE N-3 (CRC3)

BYTE N (CRC4)

LOWER BYTE COUNT

UPPER BYTE COUNT

Bus Arbitration and Timing

DM9008 powers up as a bus slave in the Reset state, in which

the receiver and transmitter are both disabled. The reset state

can be reentered under three conditions: soft reset (Stop

Command) hard reset (RST input or PC RESET por

command), or an error that shuts down the receiver or

transmitter (FIFO underflow or overflow, receive buffer ring

overflow). After initialization of registers, DM9008 is issued a

Start Command, causing it to enter idle state. Until the DMA is

required, DM9008 remains idle. Idle state is exited by a

request from FIFO in the case of a receive, transmit or a

request from the remote DMA in the case of a remote DMA

operation.

After the remote or local DMA transfer is completed, DM9008

again enters the idle state.

FIFO Burst Control

All local DMA transfers are burst transfers. Once the DMA is

activated, it will transfer an exact burst of bytes programmed in

the DCR. If there are remaining bytes in the FIFO, the next

burst will not be initiated until the FIFO threshold is exceeded.

Interleaved Local Operation

If a remote DMA transfer is initiated or in progress when a

packet is being received or transmitted, the remote DMA

transfer will be interrupted for higher priority local DMA

transfers. When the local DMA transfer is completed, the

remote DMA will rearbitrate for the bus and continue its

transfers. Note that if the FIFO requires service while a remote

DMA is in progress, the local DMA burst is appended to the

remote transfer.

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