3

MD2134

Supertex inc.

www.supertex.com

Doc.# DSFP-MD2134

C102412

Aperture DAC Characteristics

(Over operating conditions unless otherwise specified, V

Sym

Parameter

Min

Typ

Max

Units Conditions

Reso

Resolution

-

8

8

Bits

---

E

LINEAR

Linearity error

-

1.0

3.0

%

±% of FSR

E

DIFF

Differential nonlinearity error

-

0.6

1.0

%

±% of FSR

MON

Monotonicity

-

8

8

Bits

---

V

REF

External reference voltage

1.25

-

2.5

V

---

Clock and Data Input/Output Characteristics

(Over operating conditions unless otherwise specified, V

Sym

Parameter

Min

Typ

Max

Units Conditions

V

IH

Input logic high voltage

0.8V

LL

-

V

LL

V

---

V

IL

Input logic low voltage

0

-

0.2V

LL

V

---

I

IH

Input logic high current

-

-

1.0

µA

---

I

IL

Input logic low current

-1.0

-

-

µA

---

C

IN

Input capacitance

-

2.0

-

pF

---

I

OH

Output logic high current

-

-

-5.0

mA

---

I

OL

Output logic low current

-

-

5.0

mA

---

V

OH

Output logic high voltage

1.95

-

-

V

I

V

OL

Output logic low voltage

-

-

0.35

V

I

AC Electrical Characteristics

(Over operating conditions unless otherwise specified, V

Sym

Parameter

Min

Typ

Max

Units Conditions

t

ST

DAC to output setup time

-

-

10

µs

All caps 10nF, DAC = 0 to 255, settle

to 1LSB,

t

r

Output current rise time

-

2.0

3.0

ns

With 1.0Ω resistor load to V

DAC = 85, V

t

f

Output current fall time

-

2.0

3.0

t

dr

Input to output delay on rise

-

4.0

5.0

t

df

Input to output delay on fall

-

4.0

5.0

t

M

Delay time matching

-

±2.0

±3.0

ns

From PA to PB and device to device

t

J

Output jitter

-

50

-

ps

---

t

1

SDI valid to SCK setup time

0

2.0

-

ns

See serial interface timing diagram

t

2

SDI valid to SCK hold time

4.0

-

-

t

3

SCK high time % of 1/f

CLK

45

-

55

%

See serial interface timing diagram

t

4

SCK low time % of 1/f

CLK

45

-

55

t

5

CS pulse width

4.0

-

-

ns

See serial interface timing diagram

t

6

LSB SCK high to CS high

7.0

-

-

t

7

CS low to SCK high

7.0

-

-

t

8

SDO propagation delay from SCK

failing edge

-

-

10

t

9

CS high to SCK rising edge

7.0

-

-

t

10

CS high to LD rising edge

10

-

-