TS80C51RA2-VCKB datasheet(14/74 Pages) ATMEL

14 / 74 page

Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

6.2. Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a number of

ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory

location. There are two 16-bit DPTR registers that address the external memory, and a single bit called

DPS = AUXR1/bit0 (See Table 4.) that allows the program code to switch between them (Refer to Figure 3).

Figure 3. Use of Dual Pointer

Table 4. AUXR1: Auxiliary Register 1

Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for

example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’

pointer and the other one as a "destination" pointer.

AUXR1

Address 0A2H

GF3

DPS

Reset value

Symbol

Function

Not implemented, reserved for future use.a

User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active

value will be 1. The value read from a reserved bit is indeterminate.

GF3 will not be available on first version of the RC devices.

DPS

Data Pointer Selection.

DPS

Operating Mode

DPTR0 Selected

DPTR1 Selected

GF3

This bit is a general purpose user flagb.

External Data Memory

AUXR1(A2H)

DPS

DPH(83H) DPL(82H)

DPTR0

DPTR1

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