XRP9710 datasheet(21/36 Pages) EXAR

21 / 36 page

XRP9710 and XRP9711

Dual 6A Programmable Power Module

21/36

Rev. 1.0.1

coefficients the PID also uses the VIN voltage

to provide a feed forward function.

The XRP9710/1 DPWM includes a special delay

timing loop that provides a timing resolution

that is 16 times the master oscillator

frequency (103MHz) for a timing resolution of

607ps for both the driver pulse width and dead

time delays. The DWPM produces the Gate

High (GH) and Gate Low (GL) signals for the

driver. The maximum and minimum on-times

and dead time delays are programmable by

configuration resisters.

To provide current information, the output

inductor current is measured by a differential

amplifier that reads the voltage drop across

the RDS of the lower FET during its on time.

There are two selectable ranges, a low range

with a gain of 8 for a +20mV to -120 mV

range, and a high range with a gain of 4 for a

+40mV to -280mV range. The optimum range

to use will depend on the maximum output

current and the RDS of the lower FET. The

measured voltage is then converted to a

digital value by the current ADC block. The

resulting current value is stored in a readable

PWM to PFM transitions should occur.

PFM mode loop

The XRP9710/1 has a PFM loop that can be

enabled to improve efficiency at light loads.

By reducing switching frequency and operating

in the discontinuous conduction mode (DCM),

both switching and I2R losses are minimized.

Figure 23 shows a functional diagram of the

PFM logic.

# Cycles Reg

Default = 20

PFM Current

Threshold Reg

A<B

IADC

CHx Fsw

A<B

VREF HIGH

VREF

VREF LOW

VOUT

PFM EXIT

TRIGGER PULSE

PFM MODE

PWM MODE

COUNTER

Clear

Clk

Figure 23 PFM Enter/Exit Functional Diagram

The PFM loop works in conjunction with the

PWM loop and is entered when the output

current falls below a programmed threshold

level for a programmed number of cycles.

When PFM mode is entered, the PWM loop is

disabled and instead, the scaled output

voltage is compared to Vref with a window

comparator. The window comparator has three

thresholds; normal (Vref), high (Vref +

%high) and low (Vref - %low). The %high and

%low values are programmable and track

Vref.

In PFM mode, the normal comparator is used

to regulate the output voltage. If the output

voltage falls below the Vref level, the

comparator is activated and triggers the

DPWM to start a switching cycle. When the

high side FET is turned on, the inductor

current ramps up which charges up the output

capacitors and increases their voltage. After

the completion of the high side and low side

on-times, the lower FET is turned off to inhibit

any inductor reverse current flow. The load

current then discharges the output capacitors

until the output voltage falls below Vref and

the normal comparator is activated. This

triggers the DPWM to start the next switching

cycle. The time from the end of the switching

cycle to the next trigger is referred to as the

dead zone.

When PFM mode is initially

entered the switching duty cycle is equal to

the steady-state PWM duty cycle. This will

cause the inductor ripple current to be the

same level that it was in PWM mode. During

operation the PFM duty cycle is calculated

based on the ratio of the output voltage to

VCC.

This method ensures that the output

voltage ripple is well controlled and is much

lower than other architectures which use a

“burst” methodology.

If the output voltage goes outside the

high/low windows, PFM mode is exited and the

PWM loop is reactivated.

Although the PFM mode is effective at

improving efficiency at light load, at very light

loads the dead zone time can increase to the

point where the switching frequency can enter

the audio hearing range. When this happens

some components, like the output inductor

and ceramic capacitors, can emit audible

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