MCP3914 datasheet(21/80 Pages) MICROCHIP

21 / 80 page

 2013 Microchip Technology Inc.

DS20005216A-page 21

MCP3914

4.0

TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this data sheet. The following terms are

defined:

• MCLK – Master Clock

• AMCLK – Analog Master Clock

• DMCLK – Digital Master Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

• Offset Error

• Gain Error

• Integral Non-Linearity Error

• Signal-to-Noise Ratio (SNR)

• Signal-To-Noise Ratio And Distortion (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3914 Delta-Sigma Architecture

• Idle Tones

• Dithering

• Crosstalk

• PSRR

• CMRR

• ADC Reset Mode

• Hard Reset Mode (RESET = 0)

• ADC Shutdown Mode

• Full Shutdown Mode

• Measurement Error

4.1

MCLK – Master Clock

This is the fastest clock present on the device. This is

the frequency of the crystal placed at the OSC1/OSC2

inputs when CLKEXT = 0, or the frequency of the

clock input at the OSC1/CLKI when CLKEXT = 1. See

Figure 4-1.

4.2

AMCLK – Analog Master Clock

AMCLK is the clock frequency that is present on the

analog portion of the device, after prescaling has

occurred via the CONFIG0 PRE<1:0> register bits (see

Equation 4-1). The analog portion includes the PGAs

and the delta-sigma modulators.

EQUATION 4-1:

FIGURE 4-1:

Clock Sub-Circuitry.

4.3

DMCLK – Digital Master Clock

This is the clock frequency that is present on the digital

portion of the device, after prescaling and division by

four (Equation 4-2). This is also the sampling fre-

quency, which is the rate at which the modulator out-

puts are refreshed. Each period of this clock

corresponds to one sample and one modulator output.

See Figure 4-1.

EQUATION 4-2:

4.4

DRCLK – Data Rate Clock

This is the output data rate, i.e., the rate at which the

ADCs output new data. Each new data is signaled by a

data ready pulse on the DR pin.

This data rate is depending on the OSR and the

prescaler with the formula in Equation 4-3.

EQUATION 4-3:

TABLE 4-1:

MCP3914 OVERSAMPLING

RATIO SETTINGS

Config.

Analog Master Clock

Prescale

PRE<1:0>

AMCLK = MCLK/1 (default)

AMCLK = MCLK/2

AMCLK = MCLK/4

AMCLK = MCLK/8

AMCLK

MCLK

PRESCALE

-------------------------------

DMCLK

AMCLK

---------------------

MCLK

PRESCALE



----------------------------------------

DRC LK

DMC LK

OSR

----------------------

AMCLK

4OSR



---------------------

MCLK

OSR

PRESCALE



-----------------------------------------------------------

MCP3914 датащи(PDF) 21 Page - Microchip Technology

MCP3914 датащи(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL