MSP3410D datasheet(72/83 Pages) MICRONAS

72 / 83 page

MSP 34x0D

PRELIMINARY DATA SHEET

Micronas

tI2S3

I2S-Data Setup Time

before Rising Edge of Clock

I2S_CL,

I2S_DA_OUT

200

CL = 30 pF

tI2S4

I2S-Data Hold Time

after Falling Edge of Clock

180

CL = 30 pF

tI2S5

I2S-Word Strobe Setup Time

before Rising Edge of Clock

I2S_CL,

I2S_WS

200

CL = 30 pF

tI2S6

I2S-Word Strobe Hold Time

after Falling Edge of Clock

180

CL = 30 pF

Analog Ground

VAGNDC0

AGNDC Open Circuit Voltage

MSP 34x0D version A1 to B4

MSP 34x0D version C5 and later

AGNDC

3.63

3.67

3.73

3.77

3.83

3.87

Rload ≥10 MΩ

RoutAGN

AGNDC Output Resistance

125

180

Ω

3 V

≤ V

AGNDC ≤ 4 V

Analog Input Resistance

RinSC

SCART Input Resistance

from TA = 0 to 70 °C

SCn_IN_s1)

Ω

fsignal = 1 kHz, I = 0.05 mA

RinMONO

MONO Input Resistance

from TA = 0 to 70 °C

MONO_IN

1524

35k

Ω

fsignal = 1 kHz, I = 0.1 mA

Audio Analog-to-Digital-Converter

VAICL

Effective Analog Input Clipping

Level for Analog-to-Digital-

Conversion

SCn_IN_s,1)

MONO_IN

2.00

2.25

VRMS

fsignal = 1 kHz

SCART Outputs

RoutSC

SCART Output Resistance

at Tj = 27 °C

from TA = 0 to 70 °C

SCn_OUT_s1)

200

330

460

500

Ω

fsignal = 1 kHz, I = 0.1 mA

dVOUTSC

Deviation of DC-Level at SCART

Output from AGNDC Voltage

−70

+70

ASCtoSC

Gain from Analog Input

to SCART Output

SCn_IN_s1)

MONO_IN

→

SCn_OUT_s1)

−1.0

+0.5

fsignal = 1 kHz

frSCtoSC

Frequency Response from Analog

Input to SCART Output

bandwidth: 0 to 20000 Hz

−0.5

+0.5

with respect to 1 kHz

VoutSC

Effective Signal Level at

SCART-Output during full-scale

digital input signal from DSP

SCn_OUT_s1)

1.8

1.9

2.0

VRMS

fsignal = 1 kHz

1) “n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

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