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ML7066 датащи(PDF) 5 Page - LAPIS Semiconductor Co., Ltd. |
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ML7066 датащи(HTML) 5 Page - LAPIS Semiconductor Co., Ltd. |
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5 / 29 page ![]() FEDL7066-01 ML7066 5/29 TX/RX Data Related Pins Pin No. Pin Name Attribute/ value at reset I/O Active Level Description 4 DIO I IO H or L Data input/output pin (Initial value is Low when switch the state from input to output) 6 DCLK L O P or N Data clock output pin Regulator Related Pins Pin No. Pin Name Attribute/ value at reset I/O Active Level Description 33 VREG_OUT – – – Power supply output pin for the RF block (Typ. 2.2V) Do not use this pin for purposes other than RF power supply. 35 VREG_CORE – – – Power supply monitor pin for the core (Typ. 2.2V) Do not use this pin for purposes other than monitoring purpose. Decuple this pin to ground with capacitor. (*1) 36 VBG – – – Back bias pin (Capacitance connection) Decuple this pin to ground with capacitor. (*1) 37 REGPDIN L ID – Regulator power down pin Always fix this pin to “L” input in normal operation. *1: Please refer reference circuit. |
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