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ML610Q419C датащи(PDF) 37 Page - LAPIS Semiconductor Co., Ltd. |
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ML610Q419C датащи(HTML) 37 Page - LAPIS Semiconductor Co., Ltd. |
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37 / 38 page ![]() FEDL610Q419-07 ML610Q419/ML610Q419C 37/38 REVISION HISTORY Document No. Date Page Description Previous Edition Current Edition FEDL610Q419-1 Dec.26.2011 – – Formally edition 1.0 FEDL610Q419-2 Jan.11.2012 35 35 Changed figure of package dimensions. FEDL610Q419-3 Jun.5.2012 3 3 Changed part number of TQFP. FEDL610Q419-4 Sep.4.2012 21 21 Changed parameter of data retention. Changed parameter of 1-word (16 bits) write time FEDL610Q419-05 July.25.2014 All All Change header and footer 3 4 Change from "Shipment" to " Product name – Supported Function " - 22 Add CLOCK GENERATION CIRCUIT OPERATING CONDITIONS 22 23 Change "RESET" to "Reset pulse width (PRST)" , " Power-on reset activation power rise time (TPOR )" and “Low level reset detection time(TLLR)”. 22 23 Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (1/5)’s note No.2 24 25 Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (3/5)’s note No.3 27 28 Correct the CGL’s value and the CDL’s value of MEASURING CIRCUIT 1 FEDL610Q419-06 May.13,2015 2 2 Corrected a typo. “100kbps@1MHz HSCLK” is corrected to 100kbps@4MHz HSCLK. 30 30 Corrected a typo. 36 36 Change PKG 3,4,21 23 to 27 30 to 35 3,4,21 23 to 27 30 to 35 Delete wide range temperature version (P version) FEDL610Q419-07 Oct.28.2015 22 22 Correct CLOCK GENERATION CIRCUIT OPERATING CONDITIONS 23 23 Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (1/5)’s note No.2 25 25 Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (3/5)’s note No.3 28 28 Correct the CGL’s value and the CDL’s value of MEASURING CIRCUIT 1 |
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