MCP3910 datasheet(41/86 Pages) MICROCHIP

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DS20005116B-page 41

MCP3910

5.11

Data Ready Status Bits

In addition to the Data Ready pin indicator, the

MCP3910 device includes a separate data ready status

bit for each channel. Each ADC channel CHn is

associated to the corresponding DRSTATUS<n> that

can be read at all times in the STATUSCOM register.

These status bits can be used to synchronize the data

retrieval, in case the DR pin is not connected (see

Section 6.8

“ADC

Channels

Latching

and

Synchronization”

The DRSTATUS<1:0> bits are not writable; writing on

them has no effect. They have a default value of '1',

which indicates that the data of the corresponding ADC

is not ready. This means that the ADC output register

has not been updated since the last reading (or since

the last reset). The DRSTATUS bits take the '0' state,

once the ADC channel register is updated (which hap-

pens at a DRCLK rate). A simple read of the STATUS-

COM register clears all the DRSTATUS bits to their

default value ('1').

In the case of DR_LINK = 1, the DRSTATUS<1:0> bits

are all updated synchronously with the most lagging

channel, in the same time the data ready pulse is

generated. In case of DR_LINK = 0, each DRSTATUS

bit is updated independently and synchronously with its

corresponding channel.

5.12

Data Ready Link

There are two modes defined with the DR_LINK bit in

the STATUSCOM register that control the data ready

pulses. The position of the data ready pulses varies

with respect to this mode, to the OSR<2:0> and to the

PHASE register settings. Figure 5-9 represents the

behavior of the Data Ready pin with the two DR_LINK

configurations.

• DR_LINK = 0: Both data ready pulses from ADC

Channel 0 and ADC Channel 1 are output on the

DR pin.

• DR_LINK = 1 (Recommended and Default mode):

Only the data ready pulses from the most lagging

ADC between all the active ADCs are present on

the DR pin.

The lagging ADC data ready position depends on the

PHASE0/1 registers, the PRE<1:0> and the OSR<2:0>

settings. In this mode, the active ADCs are linked

together, so their data is latched together when the

lagging ADC output is ready. For power metering

applications, DR_LINK = 1 is recommended (Default

mode); it allows the host MCU to gather all channels

synchronously within a unique interrupt pulse and it

ensures that all channels have been latched at the

same time, so that no data corruption is happening.

FIGURE 5-9:

DR_LINK Configurations.

5.13

Digital System Offset and Gain

Errors

The MCP3910 incorporates two sets of additional

registers per channel to perform system digital offset

and gain error calibration. Each channel has its own set

of associated registers that will modify the output result

of the channel, if calibration is enabled. The gain and

offset calibrations can be enabled or disabled through

two

configuration

bits

(EN_OFFCAL

and

EN_GAINCAL). These two bits enable or disable

system calibration on all channels at the same time.

When both calibrations are enabled, the output of the

ADC is modified per Equation 5-8. These calibrations

are not effective in 2-Wire Interface mode.

EQUATION 5-8:

DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS

CALCULATIONS

One DRCLK period

(OSR times DMCLK periods)

DR_LINK =

Only the most lagging data ready is present

All channels are latched together at DR falling edge

DR_LINK =

All channels data ready

are present

Data ready pulse

from CH1

Data ready pulse from

CH1 channel (reference)

PHASE =

PHASE <

PHASE >

Data ready pulse from

most lagging ADC channel

(here CH0 channel lags)

Data ready pulse from

most lagging ADC channel

Data ready pulse from CH0

channel if PHASE <

DATA_CHn post

cal

–



DATA_CHn pre

cal

–

 OFFCAL_CHn



GAINCAL_CHn





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