поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

LM4931 датащи(PDF) 21 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
номер детали LM4931
подробное описание детали  Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers
PDF  47 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM4931 датащи(HTML) 21 Page - National Semiconductor (TI)

Back Button LM4931 Datasheet HTML 17Page - National Semiconductor (TI) LM4931 Datasheet HTML 18Page - National Semiconductor (TI) LM4931 Datasheet HTML 19Page - National Semiconductor (TI) LM4931 Datasheet HTML 20Page - National Semiconductor (TI) LM4931 Datasheet HTML 21Page - National Semiconductor (TI) LM4931 Datasheet HTML 22Page - National Semiconductor (TI) LM4931 Datasheet HTML 23Page - National Semiconductor (TI) LM4931 Datasheet HTML 24Page - National Semiconductor (TI) LM4931 Datasheet HTML 25Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 47 page
background image
Clock Divider Configuration Registers
This register is used to control the multiplexers in the clock module.
DEFAULT CHART FOR CLK_MUX (08h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
CLK_MUX (08h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
0
PLL_INPUT
Programs the PLL input multiplexer to select. (Note 12)
PLL_INPUT
PLL Input Source
0
MCLK
1I
2S Input Clock
1
FAST_CLOCK
If set the master clock is divided by two, for example allowing for a
24.576MHz or PCI clock to be used. (Note 12, 15)
FAST_CLOCK
MCLK Frequency
0
Normal
1
Divided by 2
2
AUDIO_CLK_SEL
Selects which clock is passed to the audio sub-system: (Note 12)
AUDIO_CLK_SEL
Audio Sub-system
Input Source
0
PLL Output
1
MCLK / MCLK/2
3
VOICE_CLK_SEL
Selects which clock is passed to the voice sub-system: (Note 12)
VOICE_CLK_SEL
Audio Sub-system
Input Source
0
PLL Output
1
MCLK / MCLK/2
4
PLL_DISABLE
Powers down the PLL if it is not required.
6:5
Q_DIV
Programs the Q divider (divides from the PLL output frequency of
12.288MHz).
6:5
Divide Value
00
12 (1.024MHz/8kHz)
01
8 (1.536MHz/12kHz)
10
6 (2.048MHz/16kHz)
11
4 (3.072MHz/24kHz)
7
RSVD
RESERVED (Note 14)
Note 15: For inputs greater than 50Mhz, the input clock divider FAST_CLOCK should be set.
www.national.com
21



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com