tions when the supply is less than 2.8V. Do not leave the EN

pin floating. Do not tie EN pin to V

LM3671-ADJ (V

OUT

≥ 2.5V) with a slow input supply ramp.

SOFT START

The LM3671 has a soft-start circuit that limits in-rush current

during start-up. During start-up the switch current limit is

increased in steps. Soft start is activated only if EN goes

from logic low to logic high after Vin reaches 2.8V. Soft start

is implemented by increasing switch current limit in steps of

70mA, 140mA, 280mA and 1020mA (typ. switch current

limit). The start-up time thereby depends on the output ca-

pacitor and load current demanded at start-up. Typical

start-up times with 22µF output capacitor and 300mA load

current is 400 µs and with 1mA load current its 275µs.

LDO - LOW DROP OUT OPERATION

The LM3671-ADJ can operate at 100% duty cycle (no

switching, PMOS switch completely on) for low drop out

support of the output voltage. In this way the output voltage

will be controlled down to the lowest possible input voltage.

The minimum input voltage needed to support the output

voltage is

V

LOAD

Load current

DSON, PFET

Drain to source resistance of

PFET switch in the triode region

INDUCTOR

Inductor resistance

Application Information

OUTPUT VOLTAGE SELECTION FOR LM3671-ADJ

The output voltage of the adjustable parts can be pro-

grammed through the resistor network connected from V

OUT

to FB then to GND. V

voltage at FB equal to 0.5V. The resistor from FB to GND

(R2) should be 200 k

Ω to keep the current drawn through

this network well below the 16 µA quiescent current level

(PFM mode) but large enough that it is not susceptible to

noise. If R2 is 200 k

Ω, and given the V

through the resistor feedback network will be 2.5 µA.

The formula for output voltage selection is:

•

V

•

V

•

R1: feedback resistor from V

•

R2: feedback resistor from FB to GND

For any output voltage greater than or equal to 0.8V a zero

must be added around 45 kHz for stability. The formula for

calculation of C1 is:

For output voltages between 0.7 and 0.8V and output volt-

ages higher than 2.5V a pole must be placed at 45 kHz as

well. The lowest output voltage possible is 0.7V. At low

output voltages the duty cycle is very small; in addition as the

input voltage increases the duty cycle decreases even fur-

ther. Since the duty cycle is so low it is very susceptible to

noise. C1 and C2 act as noise filters at this point rather than

frequency poles and zeroes. If the pole and zero are at the

same frequency the formula for calculation of C2 is:

The formula for location of zero and pole frequency created

by adding C1,C2 are given below. It can be seen that by

adding C1, a zero as well as a higher frequency pole is

introduced.

See the "LM3671-ADJ configurations for various V

table.These values are subject to change when the LM3671-

ADJ part is released.

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