Philips Semiconductors

Product data sheet

PCA9518

2004 Sep 29

4

FUNCTIONAL DESCRIPTION

The PCA9518 BiCMOS integrated circuit is a five way hub repeater,

increments of five with only one repeater delay and no functional

degradation of system performance.

The PCA9518 BiCMOS integrated circuit contains five

multi-directional, open drain buffers specifically designed to support

during arbitration or clock stretching, the PCA9518 acts like a pair of

non-inverting, open drain buffers, one for SDA and one for SCL.

Enable

The enable pins EN1 through EN4 are active-HIGH and have

internal pull-up resistors. Each enable pin ENn controls its

associated SDAn and SCLn ports. When LOW, the ENn pin blocks

the inputs from SDAn and SCLn, as well as disabling the output

drivers on the SDAn and SCLn pins. The enable pins should only

change state when both the global bus and the local port are in an

idle state to prevent system failures.

The active-HIGH enable pins allow the use of open drain drivers

which can be wire-ORed to create a distributed enable where either

centralized control signal (master) or spoke signal (submaster) can

enable the channel when it is idle.

Expansion

The PCA9518 includes 4 open drain I/O pins used for expansion.

Two expansion pins, EXPSDA1 and EXPSDA2 are used to

communicate the internal state of the serial data within each hub to

the other hubs. The EXPSDA1 pins of all hubs are connected

together to form an open-drain bus. Similarly, all EXPSDA2 pins,

EXPSCL1 pins, and all EXPSCL2 pins are connected together

forming a 4-wire bus between hubs.

When it is necessary to be able to deselect every port, each

expansion device only contributes 4 ports which can be enabled or

disables because the fifth does not have an enable pin.

one PCA9518 is used.

provide the logic HIGH levels on the Buffered bus. (Standard

of these pull-up resistors depends on the system, but each side of

the repeater must have a pull-up resistor. This part is designed to

work with standard mode (0 to 100 kHz) and fast mode (0 to

devices and multiple masters are possible. Please see Application

Note AN255

additional information on sizing resistors.

APPLICATION INFORMATION

A typical application is shown in Figure 4. In this example, the

connected to a 3.3 V or 5 V bus. All buses run at 100 kHz unless

slave 3, 4 and 5 are isolated from the bus. Then the master bus and

slave 1, 2 and 6 can run at 400 kHz.

Any segment of the hub can talk to any other segment of the hub.

Bus masters and slaves can be located on any segment with 400 pF

load allowed on each segment.

The PCA9518 is 5 V tolerant so it does not require any additional

circuitry to translate between the different bus voltages.

When one port of the PCA9518 is pulled LOW by a device on the

drives the EXPXXX1 line LOW, when the EXPXXX1 voltage is less

PCA9518 which is typically 0.5 V.

In order to illustrate what would be seen in a typical application, refer

to Figure 5. If the bus master in Figure 4 were to write to the slave

through the PCA9518, we would see the waveform shown in Figure

preceding each clock LOW to HIGH transition and proceeding each

data LOW to HIGH transition for the master. The foot height is the

difference between the LOW level driven by the master and the

higher voltage LOW level driven by the PCA9518 repeater. Its width

corresponds to an effective clock stretching coming from the

PCA9518 which delays the rising edge of the clock. That same

magnitude of delay is seen on the rising edge of the data. The foot

on the rising edge of the data is extended through the 9th clock

pulse as the PCA9518 repeats the acknowledge from the slave to

the

∼0.5 V level generated by the PCA9518. The SDA at the slave

has a particularly interesting shape during the 9th clock cycle where

the slave pulls the line below the value driven by the PCA9518

during the acknowledge and then returns to the PCA9518 level

creating a foot before it completes the LOW to HIGH transition. SDA

lines other than the one with the master and the one with the slave

have a uniform LOW level driven by the PCA9518 repeater.

The other four waveforms are the expansion bus signals and are

included primarily for timing reference points. All timing on the

expansion bus that is driven LOW whenever any SDA pin falls

whenever any pin is

≤0.4 V. EXPSCL1 is the expansion bus that is

is the expansion bus that is driven LOW whenever any SCL pin is

≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the

last one being held below 0.4 V by an external driver starts to rise.

The last SDA to rise above 0.4 V is held down by the PCA 9518 to

∼0.5 V until after the delay of the circuit which determines that it was

the last to rise, then it is allowed to rise above the

∼0.5 V level driven

by the PCA9518. Considering the bus 0 SDA to be the last one to go

above 0.4 V, then the EXPSDA1 returns to HIGH after the

EXPSDA2 is HIGH and either the bus 0 SDA rise time is 1

µs or,

both EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines

are allowed to rise. The same description applies for the EXPSCL1,

EXPSCL2, and SCL pins.

3.

XXXX is SDA1, SDA2, SCL1, or SCL2

XXX is SDA or SCL