CDC304

OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

SCAS325A – JULY 1990 – REVISED NOVEMBER 1995

4

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

CLK

Q

3.5 V

VOL

0.3 V

1.3 V

tsu

From Output

Under Test

LOAD CIRCUIT

Test Point

CLR

or

PRE

1.3 V

1.3 V

1.3 V

VOH

CL

(see Note A)

tPLH

tPHL

RL

tw

1.3 V

3.5 V

0.3 V

NOTES: A. CL includes probe and jig capacitance.

B. Input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms