13/19

REV1A

Application Information (Continued)

and serial clock (SCL). The XR18910 works as a slave and

supports both standard mode transfer rates (100 kbps) and

■

■

A start condition

■

■

A slave address cycle

■

■

Zero, one, or two data cycles - depending on the XR18910

register accessed

■

■

A stop condition

Start Condition

The master initiates data transfer by generating a start

condition. The start condition is when a high-to-low transition

occurs on the SDA line while SCL is high, as shown in

Figure 21.

Slave Address Cycle

After the start condition, the first byte sent by the master

is the 7-bit address and the read/write direction bit R/W

on the SDA line. If the address matches the XR18910’s

internal fixed address, the XR18910 will respond with an

acknowledge by pulling the SDA line low for one clock cycle

while SCL is high.

Data Cycle

After the master detects this acknowledge, the next byte

transmitted by the master is the sub-address. This 8-bit

sub-address contains the address of the register to access.

The XR18910 Register List is shown in Table 1. Depending

on the register accessed, there will be up to two additional

data bytes transmitted by the master. Refer to the “Byte of

Parameter” column in the Register Table. The XR18910 will

respond to each write with an acknowledge.

Stop Condition

To signal the end of the data transfer, the master generates

a stop condition by pulling the SDA line from low to high

while the SCL line is high, as shown in Figure 21.

Figures 22 and 23 illustrate a write and a read cycle. For

S

SLAVE

ADDRESS

W

A

REGISTER

ADDRESS

A

nDATA

A

P

NOTES:

White Block = host to XR18910, Orange Block = XR18910 to host.

Figure 22. Master Writes to Slave (XR18910)

S

SLAVE

ADDRESS

W A

REGISTER

ADDRESS

A S

SLAVE

ADDRESS

R A nDATA A

LAST

DATA

NA P

NOTES:

White Block = host to XR18910, Orange Block = XR18910 to host.

Figure 23. Master Reads from Slave (XR18910)

The XR18910 uses a 7-bit address space. For the standard

XR18910, the default address is 0x67 (0110 111). There

are three alternative addresses available to help insure that

the XR18910 can be identified from the other devices on

available.

Orderable Part Number

XR18910IL-67

XR18910IL-66

XR18910IL-65

XR18910IL-64

A read or write transaction is determined by bit-0 of the

is ’0’, then it is a write transaction. If bit-0 is ’1’, then it is a

read transaction.

slave address. The sub-address contains the XR18910

register address being accessed. Table 1 illustrates the

available XR18910 register addresses.

will set the SCL signal back to its idle state (HIGH).

XR20M1280

7

REV. 1.0.0

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

1.0 FUNCTIONAL DESCRIPTIONS

1.1

CPU Interface

selected via the I2C/SPI# input pin.

1.1.1

interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock

and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400

SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-

address that contains the address of the register to access. The XR20M1280 responds to each write with an

acknowledge (SDA driven LOW by XR20M1280 for one clock cycle when SCL is HIGH). If the TX FIFO is full,

the XR20M1280 will respond with a negative acknowledge (SDA driven HIGH by XR20M1280 for one clock

contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See

SDA

SCL

S

P

START condition

STOP condition

SW

A

A

AP

SLAVE

ADDRESS

REGISTER

ADDRESS

nDATA

White block: host to UART

Grey block: UART to host

SW

A

AR

SLAVE

ADDRESS

REGISTER

ADDRESS

White block: host to UART

Grey block: UART to host

A

S

SLAVE

ADDRESS

nDATA

A

NA

P

LAST DATA

2

XR

18910