ADE3300 datasheet(27/88 Pages) STMICROELECTRONICS

номер детали	ADE3300

подробное описание детали	LCD Display Engines with Integrated DVI, ADC and YUV Ports

PDF	88 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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ADE3XXX

HDCP Block

2.6

HDCP Block

The HDCP block implements the datapath decryption block of the HDCP content protection scheme

of DVI. Please refer to the HDCP Specification 1.0 for details. The state machines of the HDCP

specification are split between the external microcontroller and this block. Only the high speed and

data intensive cryptographic functions are implemented in this block to maintain maximum system

level flexibility.

DVI_PLL_6

0x0486

R/W

[7:6]

[5:4]

[3:2]

[1:0]

0x0

Strobe [16:19] Delay Adjustment

0x0: Normal

0x1: Slow

0x2: Fast

0x3: Reserved

DVI_PLL_7

0x0487

R/W

[7:6]

[5:4]

[3:2]

[1:0]

0x0

Strobe [20:23] Delay Adjustment

0x0: Normal

0x1: Slow

0x2: Fast

0x3: Reserved

DVI_PLL_8

0x0488

R/W

[7:6]

[5:4]

[3:2]

[1:0]

0x0

Strobe [24:27] Delay Adjustment

0x0: Normal

0x1: Slow

0x2: Fast

0x3: Reserved

DVI_PLL_9

0x0489

[7:6]

Reserved

R/W

[5]

0x0

Test Enable (normal operation = 0)

R/W

[4]

0x0

Strobe Delay Adjustment Step

0: 45pS (default)

1: 72pS

R/W

[3:2]

0x0

Strobe 29 Adjust

0: Normal

1: Slower

2: Faster

3: Reserved

R/W

[1:0]

0x0

Strobe 28 Adjust

R/W

[3:2]

[1:0]

0x0

Strobe [28:29] Delay Adjustment

0x0: Normal

0x1: Slow

0x2: Fast

0x3: Reserved

DVI_PLL_10

0x048A

[7]

Reserved

[6:4]

Test Output DVIPLL[79:77]

[3:0]

PLL Range Status

[3:0]

0x0

PLL Range Status

Table 9: DVI Registers (Sheet 5 of 5)

Addr

Mode

Bits

Default

Description

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