LTC4355 datasheet(13/24 Pages) LINEAR

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LTC4420

4420f

For more information www.linear.com/LTC4420

applicaTions inForMaTion

2. To provide default battery backup monitoring and dis-

connect in systems where V2TEST and V2DIS are not

actively driven. V2TEST and V2DIS are either tied high

or low in these applications.

3. To allow a system powered by OUT to shut itself down

if there is no valid input supply.

4. To support backup battery charging without having to

disconnect the battery from the system.

5. Handling exceptions such as initial power up, recov-

ery from thermal shutdown and switchover after long

intervals when V2 was not being monitored.

Configuring V2TEST and V2DIS

V2TEST controls the duration of and the time between

V2 monitoring events. It can either be tied high, low or

actively driven based on the application. The following

section explores common scenarios.

In applications where primary supply V1 is going to be

valid for long periods of time and where V2TEST can be

activelydriven,V2TESTshouldgenerallybedrivenlowand

onlypulsedhighwhenV2statusisneeded.Thisminimizes

V2-V2UV-GNDSW divider current. This scenario also

applies when V2 is a battery that slowly discharges over

time, making a V2 status update every 132s superfluous.

When operating off V2, V2TEST may be pulsed at intervals

shorter than 131s to check V2’s validity especially after

large load current spikes.

If V2TEST cannot be actively driven, it should be tied to

either V2 or OUT through a pull-up resistor. If V2 can be

reversed, tie V2TEST to OUT. Tying V2TEST high ensures

that V2 is monitored every 132s as long as V2 > 1.55V.

V2 monitoring duration is 128ms when V2 is valid and

reduces to 2ms if V2 becomes invalid. Use smaller resis-

tors in the V2-V2UV-GNDSW divider if V2 is a battery that

can develop a passivation layer when it is not being used.

Larger V2 current helps break the passivation whenever

the V2 divider is active.

In special cases where V2 needs to be monitored only

when V1 goes invalid and when battery passivation is not

an issue, tie V2TEST low.

If automatic V2 disconnect is desired when a V2 UV event

occurs, tie V2DIS low. Otherwise leave open or tie to either

OUT or V2 through a pull up resistor. If V2 can be reversed,

tie V2DIS to OUT. If V2DIS can be actively driven, driving

it low some time after a V2 UV event (output V2OK goes

low)allowssystemspoweredbyOUTtofinishactivetasks,

backup data and initiate shutdown proceedings.

Actively Driving V2TEST

In Figure 5, V2TEST is actively driven. When V1 powers up

above switchover threshold VSW1, it is qualified for 64ms

after which the V1 to OUT power path is activated. When

V2 rises above 1.55V, GNDSW is pulsed low for 128ms

and V2UV is monitored, even though V2TEST is low. V2

is found to be valid resulting in V2OK being driven high.

As long as V1 remains valid, V2 is monitored only when

V2TEST is driven high with V2 monitoring time being the

lower of either the V2TEST high time or 128ms. Figure 5

shows two such monitoring events of durations t1 and

t2 where t1 and t2 are less than 128ms. When V1 drops

below VSW1, OUT is switched to V2 and V2 validity is

refreshed by monitoring it once for 128ms independent

of the state of V2TEST. Following this, since V2 is the

only valid supply, V2 is monitored for 2ms every 132s

if V2TEST is low or for 128ms every 132s if V2TEST is

high. If V2 becomes invalid and V2DIS is low, the V2 to

OUT power path gets disabled.

V2TEST Tied Low

Figure 6 shows voltage waveforms for the case where

V2TEST is tied low. When V2 powers up above 1.55V,

GNDSWispulsedlowandV2ismonitoredoncefor128ms.

Simultaneously, the V2 to OUT power path is activated in

order to allow a system powered by OUT to power itself

up and drive V2DIS to a desired state. V2 is determined

to be valid causing V2OK to be driven high and the V2

power path to remain activated. If V2 was determined to

be invalid and V2DIS was low, V2’s power path would have

been disabled and V2OK pulled low after 128ms. Since

both V1 and V2TEST are low, V2 is monitored for 2ms

every 132s. When V1 becomes valid, OUT is switched to

V1 and V2 monitoring is halted until V1 becomes invalid.

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