SC1200 datasheet(22/60 Pages) TI

22 / 60 page

MSC1200

SBAS289E

www.ti.com

The timing diagram for supported SPI data transfers is

shown in Figure 16.

The I/O pins needed for data transfer are Data In (DIN), Data

Out (DOUT) and serial clock (SCK). The slave select (SS)

pin can also be used to control the output of data on DOUT.

The DIN pin is used for shifting data in for both master and

slave modes.

The DOUT pin is used for shifting data out for both master

and slave modes.

The SCK pin is used to synchronize the transfer of data for

both master and slave modes. SCK is always generated by

the master. The generation of SCK in master mode can be

done in SW by simply toggling the port pin, or the generation

of SCK can be accomplished by configuring the output on the

SCK pin via PASEL (SFR F2H). A list of the most common

methods of generating SCK follows, but the complete list of

clock sources can be found by referring to the PASEL SFR.

• Toggle SCK by setting and clearing the port pin.

• Memory Write Pulse (WR) which is idle high. Whenever a

external memory write command (MOVX) is executed then a

pulse is seen on P3.6. This method can be used only if CPOL

is set to ‘1’.

• Memory Write Pulse toggle version: In this mode, SCK

toggles whenever an external write command (MOVX) is

executed.

• T0_Out signal can be used as a clock. A pulse is generated

on SCK whenever Timer 0 expires. The idle state of the

signal is low, so this can be used only if CPOL is cleared to

‘0’.

• T0_Out Toggle: SCK toggles whenever Timer 0 expires.

• T1_Out signal can be used as a clock. A pulse is generated

whenever Timer 1 expires. The idle state of the signal is low,

so this can be used only if CPOL is cleared to ‘0’.

• T1_Out Toggle: SCK toggles whenever Timer 1 expires.

The SS pin can be used to control the output of data on

DOUT when the MSC1200 is in slave mode. The SS function

is enabled or disabled by the ESS bit of the SPICON SFR.

When enabled, the SS input of a slave device must be

externally asserted before a master device can exchange

data with the slave device. SS must be low before data

transactions and must stay low for the duration of the

transaction. When SS is high then data will not be shifted into

the shift register nor will the counter increment. When SPI is

enabled, SS also controls the drive of the line DOUT (P1.2).

When SS is low in slave mode, the DOUT pin will be driven

and when SS is high then DOUT will be high impedance.

The SPI generates an interrupt ECNT (AIE.2) to indicate that

the transfer/reception of the byte is complete. The interrupt

goes high whenever the counter value is equal to 8 (indicat-

ing that 8 SCKs have occurred). The interrupt is cleared on

reading or writing to the SPIDATA register. During the data

transfer, the actual counter value can be read from the

SPICON SFR.

Power Down

The SPI is powered down by the PDSPI bit in the power

control register (PDCON). This bit needs to be cleared to

enable the SPI function. When the SPI is powered down the

pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose

I/O pins.

Application Flow

Explained below are the steps of the typical application

usage flow of SPI in master and slave mode:

Master Mode Application Flow

1. Configure the port pins.

2. Configure the SPI.

3. Assert SS to enable slave communications (if applicable).

4. Write data to SPIDATA.

5. Generate 8 SCKs.

6. Read the received data from SPIDATA.

FIGURE 16. SPI Timing Diagram.

1) SS Asserted

2) First SCK Edge

3) CNTIF Set (dependent on CPHA bit)

4) SS Negated

SCK Cycle #

MSB

54321

LSB

MSB

54321

LSB

Slave CPHA = 0 Transfer in Progress

123

Slave CPHA = 1 Transfer in Progress

Sample Input

(CPHA = 0) Data Out

(CPHA = 1) Data Out

Sample Input

SS to Slave

SCK (CPOL = 0)

SCK (CPOL = 1)

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