AS4C2M32S datasheet(9/53 Pages) ALSC

9 / 53 page

AS4C2M32S

Confidential

Rev. 3.0

Dec. /2012

Figure 9. Read to Precharge (CAS# Latency = 2, 3)

CLK

ADDRESS

CAS# latency=2

tCK2, DQ

CAS# latency=3

tCK3, DQ

COMMAND

tRP

NOP

Precharge

NOP

Bank(s)

NOP

READ A

Bank,

Col A

DOUT A0 DOUT A1

DOUT A3

DOUT A2

DOUT A1

DOUT A0

DOUT A3

Bank

Row

Activate

NOP

Don’t Care

Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A7 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after the

read operation. Once this command is given, any subsequent command cannot occur within a time delay

of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and

the auto precharge function is ignored.

Write command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active row in

an active bank. The bank must be active for at least tRCD (min.) before the Write command is issued.

During write bursts, the first valid data-in element will be registered coincident with the Write command.

Subsequent data elements will be registered on each successive positive clock edge (refer to the

following figure). The DQs remain with high-impedance at the end of the burst unless another command is

initiated. The burst length and burst sequence are determined by the mode register, which is already

programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column

0 and continue).

Figure 10. Burst Write Operation (Burst Length = 4)

CLK

DIN A0

DIN A1

DIN A2

DIN A3

COMMAND

NOP

WRITE A

NOP

The first data element and the write

are registered on the same clock edge

Don’t Care

A write burst without the auto precharge function may be interrupted by a subsequent Write,

BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming

from Write command can occur on any clock cycle following the previous Write command (refer to the

following figure).

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