DP7409

© NIDEC COPAL ELECTRONICS CORP.

5

Doc. No. MD-2010 Rev. K

Characteristics subject to change without notice

WRITE CYCLE LIMITS

s

t

i

n

U

x

a

M

r

e

t

e

m

a

r

a

P

l

o

b

m

y

S

s

m

5

e

m

i

T

e

l

c

y

C

e

t

i

r

W

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Reference Test Method

Min

Max

Units

(1)

Endurance

MIL-STD-883, Test Method 1033

1,000,000

Cycles/Byte

(1)

Data Retention

MIL-STD-883, Test Method 1008

100

Years

(1)

ESD Susceptibility

MIL-STD-883, Test Method 3015

2000

V

(1) (2)

A

m

0

0

1

7

1

d

r

a

d

n

a

t

S

C

E

D

E

J

p

U

-

h

c

t

a

L

Figure 1. Bus Timing

Figure 2. Write Cycle Timing

Figure 3. Start/Stop Timing

Notes:

(1)

This parameter is tested initially and after a design or process change that affects the parameter.

(2)

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tF

tLOW

tR

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK

8TH BIT

BYTE n

SCL

SDA

START CONDITION

SDA

STOP CONDITION

SCL