DP7401

© NIDEC COPAL ELECTRONICS CORP.

1

H

.

v

e

R

2

1

0

2

-

D

M

.

o

N

.

c

o

D

Characteristics subject to change without notice

Quad Digital Potentiometers

(DP) with 64 Taps and SPI Interface

FEATURES

Four linear taper digital potentiometers

64 resistor taps per potentiometer

End to end resistance 2.5k , 10k , 50k

or

100k

Potentiometer control and memory access via

SPI interface: Mode (0, 0) and (1, 1)

Low wiper resistance, typically 80

Nonvolatile memory storage for up to four

wiper settings for each potentiometer

Automatic recall of saved wiper settings at

power up

2.5 to 6.0 volt operation

Standby current less than 1µA

1,000,000 nonvolatile WRITE cycles

100 year nonvolatile memory data retention

24-lead SOIC and 24-lead TSSOP

Industrial temperature range

For Ordering Information details, see page 14.

PIN CONFIGURATION

DESCRIPTION

The

DP7401

is

four

Digital

Potentiometers

(DPs) integrated with control logic and 16 bytes

of NVRAM memory. Each DP consists of a series

of

63

resistive

elements

connected

between

two

externally

accessible

end

points.

The

tap

points between each resistive element are connected

to the wiper outputs with CMOS switches. A separate

6-bit control register (WCR) independently controls

the wiper tap switches for each DP. Associated with

each wiper control register are four 6-bit non-volatile

memory data registers (DR) used for storing up to four

wiper settings. Writing to the wiper control register or

any of the non-volatile data registers is via a SPI serial

bus. On power-up, the contents of the first data

register (DR0) for each of the four potentiometers is

automatically loaded into its respective wiper control

register.

The DP7401 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications.

FUNCTIONAL DIAGRAM

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

DP

7401

VCC

RL0

RH0

RW0

CS

WP

SI

A1

RL1

RH1

RW1

GND

NC

RL3

RH3

RW3

A0

SO

HOLD

SCK

RL2

RH2

RW2

NC

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

DP

7401

SI

A1

RL1

RH1

RW1

GND

NC

RW2

RH2

RL2

SCK

HOLD

WP

CS

RW0

RH0

RL0

VCC

NC

RL3

RH3

RW3

A0

SO

SOIC Package (W)

TSSOP Package (Y)

NONVOLATILE

DATA

REGISTERS

CONTROL LOGIC

WIPER CONTROL

REGISTERS

SPI BUS

INTERFACE

CS

SCK

SI

SO

WP