DP7269

© NIDEC COPAL ELECTRONICS CORP.

7

D

.

v

e

R

3

2

1

2

-

D

M

.

o

N

.

c

o

D

Characteristics subject to change without notice

Figure 2. Write Cycle Timing

Figure 3. Start/Stop Condition

Figure 4. Acknowledge Condition

Figure 5. Slave Address Bits

DP7269

0

1

0

1

A3

A2

A1

A0

*

A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

**

A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK

8TH BIT

BYTE n

SCL

SDA

START CONDITION

SDA

STOP CONDITION

SCL

ACKNOWLEDGE

1

START

SCL FROM

MASTER

89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER