DP7259

© NIDEC COPAL ELECTRONICS CORP.

1

Doc. No. MD-2000 Rev. H

Characteristics subject to change without notice

Quad Digital Potentiometers

(DP) with 256 Taps and 2-wire Interface

FEATURES

Four linear taper digital potentiometers

256 resistor taps per potentiometer

End to end resistance 50k

or 100k

Potentiometer control and memory access via

2-wire interface (I

Low wiper resistance, typically 100

Nonvolatile memory storage for up to four

wiper settings for each potentiometer

Automatic recall of saved wiper settings at

power up

2.5 to 6.0 volt operation

Standby current less than 1µA

1,000,000 nonvolatile WRITE cycles

100 year nonvolatile memory data retention

24-lead SOIC and 24-lead TSSOP packages

Industrial temperature range

For Ordering Information details, see page 15.

PIN CONFIGURATION

SOIC (W)

TSSOP (Y)

NC

1

24 A3

A0

2

23 SCL

NC

6

19 NC

7

18 GND

A2 11

14 A1

WP

¯¯¯ 12

13 SDA

DESCRIPTION

The

DP7259

is

four

digital

potentiometers

(DPs) integrated with control logic and 16 bytes

of NVRAM memory. Each DP consists of a series

of

resistive

elements

connected

between

two

externally accessible end points. The tap points

between each resistive element are connected to the

wiper outputs with CMOS switches. A separate 8-bit

control register (WCR) independently controls the

wiper tap switches for each DP. Associated with

each wiper control register are four 8-bit non-volatile

memory data registers (DR) used for storing up to four

wiper settings. Writing to the wiper control register or

any of the non-volatile data registers is via a 2-wire

serial bus. On power-up, the contents of the first data

register (DR0) for each of the four potentiometers

is automatically loaded into its respective wiper

control registers.

The DP7259 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications. It is available in the -40ºC to 85ºC

industrial operating temperature ranges and offered in

a 24-lead SOIC and TSSOP package.

FUNCTIONAL DIAGRAM

NONVOLATILE

DATA

REGISTERS

CONTROL LOGIC

WIPER CONTROL

REGISTERS

2-WIRE BUS

INTERFACE

SCL

SDA

WP