AX5243 datasheet(18/42 Pages) ONSEMI

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AX5243

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SYSCLK Output

The SYSCLK pin outputs either the reference clock signal

divided by a programmable power of two or the low power

oscillator clock. Division ratios from 1 to 1024 are possible.

For divider ratios > 1 the duty cycle is 50%. Bits

SYSCLK[4:0] in the PINFUNCSYSCLK register set the

divider ratio. The SYSCLK output can be disabled.

After power−up SYSCLK outputs 1/16 of the crystal

oscillator clock, making it possible to use this clock to boot

a micro−controller.

Power−on−Reset (POR)

AX5243 has an integrated power−on−reset block. No

external POR circuit is required.

After POR the AX5243 can be reset by first setting the SPI

SEL pin to high for at least 100 ns, then setting followed by

resetting the bit RST in the PWRMODE register.

After POR or reset all registers are set to their default

values.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a

fully integrated synthesizer, which multiplies the reference

frequency from the crystal oscillator to get the desired RF

frequency. The advanced architecture of the synthesizer

enables frequency resolutions of 1 Hz, as well as fast settling

times of 5 – 50

ms depending on the settings (see section AC

Characteristics). Fast settling times mean fast start−up and

fast RX/TX switching, which enables low−power system

design.

For receive operation the RF frequency is fed to the mixer,

for transmit operation to the power−amplifier.

The frequency must be programmed to the desired carrier

frequency.

The synthesizer loop bandwidth can be programmed, this

serves three purposes:

1. Start−up time optimization, start−up is faster for

higher synthesizer loop bandwidths

2. TX spectrum optimization, phase−noise at

300 kHz to 1 MHz distance from the carrier

improves with lower synthesizer loop bandwidths

3. Adaptation of the bandwidth to the data−rate. For

transmission of FSK and MSK it is required that

the synthesizer bandwidth must be in the order of

the data−rate.

VCO

An on−chip VCO converts the control voltage generated

by the charge pump and loop filter into an output frequency.

This frequency is used for transmit as well as for receive

operation. The frequency can be programmed in 1 Hz steps

in the FREQ registers. For operation in the 433 MHz band,

the RFDIV bit in the PLLVCODIV register must be

programmed.

The fully integrated VCO allows to operate the device in

the frequency ranges 800 – 1050 MHz and 400 – 525 MHz.

The carrier frequency range can be extended to 54 –

525 MHz and 27 – 262 MHz by using an appropriate

external inductor between device pins L1 and L2. The bit

VCO2INT in the PLLVCODIV register must be set high to

enter this mode.

It is also possible to use a fully external VCO by setting

bits VCO2INT = 0 and VCOSEL = 1 in the PLLVCODIV

desired RF frequency must be input at device pins L1 and

L2. The control voltage for the VCO can be output at device

pin FILT when using external filter mode. The voltage range

of this output pin is 0 – 1.8 V.

This mode of operation is recommended for special

applications where the phase noise requirements are not met

when using the fully internal VCO or the internal VCO with

external inductor.

VCO Auto−Ranging

The AX5243 has an integrated auto−ranging function,

which allows to set the correct VCO range for specific

frequency generation subsystem settings automatically.

Typically it has to be executed after power−up. The function

is initiated by setting the RNG_START bit in the

PLLRANGINGA or PLLRANGINGB register. The bit is

readable and a 0 indicates the end of the ranging process.

Setting RNG_START in the PLLRANGINGA register

ranges the frequency in FREQA, while setting

RNG_START in the PLLRANGINGB register ranges the

frequency in FREQB. The RNGERR bit indicates the

correct execution of the auto−ranging.

VCO auto−ranging works with the fully integrated VCO

and with the internal VCO with external inductor.

Loop Filter and Charge Pump

The AX5243 internal loop filter configuration together

with the charge pump current sets the synthesizer loop band

width. The internal loop−filter has three configurations that

can be programmed via the register bits FLT[1:0] in registers

PLLLOOP or PLLLOOPBOOST the charge pump current

can be programmed using register bits PLLCPI[7:0] in

registers PLLCPI

or PLLCPIBOOST. Synthesizer

bandwidths are typically 50 – 500 kHz depending on the

PLLLOOP or PLLLOOPBOOST settings, for details see

the section: AC Characteristics.

The AX5243 can be setup in such a way that when the

synthesizer is started, the settings in the registers

PLLLOOPBOOST and PLLCPIBOOST are applied first

for a programmable duration before reverting to the settings

in PLLLOOP and PLLCPI

. This feature enables automated

fastest start−up.

Setting bits FLT[1:0] = 00 bypasses the internal loop filter

and the VCO control voltage is output to an external loop

filter at pin FILT. This mode of operation is recommended

for achieving lower bandwidths than with the internal loop

filter and for usage with a fully external VCO.

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