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DP7140 датащи(PDF) 4 Page - Copal Electronics |
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DP7140 датащи(HTML) 4 Page - Copal Electronics |
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4 / 11 page ![]() DP7140 4 Table 7. CAPACITANCE (TA = 25 C, f = 1.0 MHz, VCC = 5 V) Test Test Conditions Symbol Max Units Input/Output Capacitance (SDA) VI/O = 0 V CI/O (Note 8) 8 pF Input Capacitance (SCL, WP) VIN = 0 V CIN (Note 8) 6 pF Table 8. POWER UP TIMING (Notes 8 and 9) Parameter Symbol Max Units Power up to Read Operation tPUR 1 ms Power up to Write Operation tPUW 1 ms 8. This parameter is tested initially and after a design or process change that affects the parameter. 9. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated. Table 9. DP TIMING Parameter Symbol Min Max Units Wiper Response Time After Power Supply Stable tWRPO 50 s Wiper Response Time: SCL falling edge after last bit of wiper position data byte to wiper change tWR 20 s Table 10. ENDURANCE Parameter Reference Test Method Symbol Min Max Units Endurance MIL STD 883, Test Method 1033 NEND 2,000,000 Cycles Data Retention MIL STD 883, Test Method 1008 TDR 100 Years Table 11. A.C. CHARACTERISTICS (VCC =+2.5V to +5.5 V, 40 C to +85 C unless otherwise specified.) Parameter Symbol Min Typ Max Units Clock Frequency fSCL 400 kHz Clock High Period tHIGH 600 ns Clock Low Period tLOW 1300 ns Start Condition Setup Time (for a Repeated Start Condition) tSU:STA 600 ns Start Condition Hold Time tHD:STA 600 ns Data in Setup Time tSU:DAT 100 ns Data in Hold Time tHD:DAT 0 ns Stop Condition Setup Time tSU:STO 600 ns Time the bus must be free before a new transmission can start tBUF 1300 ns WP Setup Time tSU:WP 0 s WP Hold Time tHD:WP 2.5 s SDA and SCL Rise Time tR 300 ns SDA and SCL Fall Time tF 300 ns Data Out Hold Time tDH 100 ns Noise Suppression Time Constant at SCL, SDA Inputs TI 50 ns SLC Low to SDA Data Out and ACK Out tAA 1 s Non Volatile Write Cycle Time tWR 4 10 ms |
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