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DS1830AS датащи(PDF) 7 Page - Dallas Semiconductor |
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DS1830AS датащи(HTML) 7 Page - Dallas Semiconductor |
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7 / 7 page ![]() D1830/A 7 of 7 NOTES: 1. All voltages are referenced to ground. 2. PBRST is internally pulled up to VCC with an internal impedance of 40kW typical. 3. Measured with PBRST = VCC and RST1 , RST2 , and RST3 open. 4. Measured with outputs open and all inputs at VCC or Ground (except TD and TOL can be floating). 5. Noise Immunity - Pulses < 2ms at VCC TP minimum will not cause a reset. 6. The t F value is for reference in defining values for tRPD and should not be considered a requirement for proper operation or use of the device. 7. See t RST1, tRST2, and tRST3 for specific tRPU AC timing parameters. ORDERING INFORMATION PART # PIN PACKAGE TEMP TYPE DS1830 8-DIP 300-MIL -40 °C to +85°C 5V Reset Sequencer DS1830S 8-SO 150-MIL -40 °C to +85°C 5V Reset Sequencer DS1830U 8-µSOP 118-MIL -40 °C to +85°C 5V Reset Sequencer DS1830A 8-DIP 300-MIL -40 °C to +85°C 3.3V Reset Sequencer DS1830AS 8-SO 150-MIL -40 °C to +85°C 3.3V Reset Sequencer DS1830AU 8-µSOP 118-MIL -40 °C to +85°C 3.3V Reset Sequencer |
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