DF1706

10

SBAS182

PIN

PIN

NAME

NUMBER

DESCRIPTION

RSV

13

Reserved, Not Used

LRIP

12

LRCIN Polarity

LRIP = H: LRCIN= H = Left Channel, LRCIN= L = Right Channel

LRIP = L: LRCIN= L = Left Channel, LRCIN = H = Right Channel

CKO

11

CLKO Output Frequency

CKO = H: CLKO Frequency = XTI/2

CKO = L: CLKO Frequency = XTI

MUTE

15

Soft Mute Control: H = Mute Off, L = Mute On

3

Input Data Format Controls

IW0

4

IW1

5

IW1

IW0

INPUT FORMAT

L

L

L

16-Bit, Standard, MSB-First, Right-Justified

L

L

H

20-Bit, Standard, MSB-First, Right-Justified

L

H

L

24-Bit, Standard, MSB-First, Right-Justified

L

H

H

24-Bit, MSB-First, Left-Justified

H

L

L

H

L

H

SRO

27

Digital Filter Roll-Off: H = Slow, L = Sharp

OW0

19

Output Data Word Length Controls

OW1

20

OW1 OW0

OUTPUT FORMAT

L

L

16-Bit, MSB-First

L

H

18-Bit, MSB-First

H

L

20-Bit, MSB-First

H

H

24-Bit, MSB-First

SF0

17

Sample Rate Selection for the Digital De-Emphasis Control

SF1

18

SF1

SF0

SAMPLING RATE

L

L

44.1kHz

L

H

Reserved, Not Used

H

L

48kHz

H

H

32kHz

DEM

16

Digital De-Emphasis: H = On, L = Off

x4

21

TABLE IV. Hardware Mode Controls.

RESET

SOFTWARE

HARDWARE

DEFAULT

FUNCTION

(MODE = H)

(MODE = L)

(Software Mode)

Input Data Format Selection

O

O

Standard Format

Input Word Length Selection

O

O

16 Bits

Output Word Length Selection

O

O

16 Bits

LRCIN Polarity Selection

O

O

Left/Right = High/Low

Digital De-Emphasis

O

O

OFF

Over Sample Ratio Control

O

O

8x

Soft Mute

O

O

OFF

Digital Attenuation

O

X

0dB, Independent L/R

Sample Rate for

De-Emphasis Function

O

O

44.1 kHz

Filter Roll-Off Selection

O

O

Sharp Roll-Off Selected

CLKO Output-Frequency Selection

O

O

Same As XTI Input

Legend: O = User Programmable, X = Not Available.

TABLE III. User-Programmable Functions for Software and

Hardware Mode.

Programmable Functions

The DF1706 includes a number of programmable features,

with most being accessible from either Hardware or Soft-

ware mode. Table III summarizes the user-programmable

functions for both modes of operation.

Hardware Mode Controls

With MODE = L, the DF1706 may be configured by

utilizing several user-programmable pins. The following is a

brief summary of the pin functions. Table IV provides more

details on setting the hardware mode controls.

input format and word length.

Pins OW0 and OW1 are used to select the output data word

length.

The DEM pin is used to enable and disable the digital de-

emphasis function. De-emphasis is only available for 32kHz,

44.1kHz, and 48kHz sample rates.

Pins SF0 and SF1 are used to select the sample rate for the

de-emphasis function.

The SRO pin is used to select the digital filter response,

either sharp or slow roll-off. Generally, sharp roll-off filter

is used.

The MUTE pin is used to enable or disable the soft mute

function.

The CKO pin is used to select the clock frequency seen at

the CLKO pin, either XTI or XTI

÷ 2.

The LRIP pin is used to select the polarity used for the audio

input left/right clock, LRCIN.

The x4 pin is used to control the over sampling ratio of the

internal digital filter, either a 8x or 4x. For instance, when fs

is 192kHz or 176.4kHz, the over sampling ratio should be 4x.

Finally, the RESV pin is not used by the current DF1706

design, but is reserved for future use.

Software Mode Controls

With MODE = H, the DF1706 may be configured by

programming four internal registers in software mode. ML

(pin 13), MC (pin 12), and MD (pin 11) make up the 3-wire

software control port, and may be controlled using DSP or

microcontroller general purpose I/O pins, or a serial port.

Table V provides an overview of the internal registers,

labeled MODE0 through MODE3 (see Table V).

See Figures 8 through 10 for more details regarding the

control port data format and timing requirements. The data

format for the control port is 16-bit, MSB-first, with Bit B15

being the MSB.

Register Addressing

A[1:0], bits B10 and B9 of the 16-bit control data word, are

used to indicate the register address to be written to by the

current control port write cycle. See Table VI for how to

address the internal registers using bits A[1:0] of registers

MODE0 through MODE3.