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UCD3138 датащи(PDF) 17 Page - Texas Instruments

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номер детали UCD3138
подробное описание детали  Highly Integrated Digital Controller for Isolated Power
PDF  89 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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UCD3138 датащи(HTML) 17 Page - Texas Instruments

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UCD3138
www.ti.com
SLUSAP2G – MARCH 2012 – REVISED SEPTEMBER 2016
Submit Documentation Feedback
Product Folder Links: UCD3138
Specifications
Copyright © 2012–2016, Texas Instruments Incorporated
Table 5-1. PMBus/SMBus/I2C Timing (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
(3)
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(4)
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(5)
Cb (pF)
t(LOW)
Clock low period
1.3
µs
t(HIGH)
Clock high period(3)
0.6
µs
t(LOW:SEXT)
Cumulative clock low slave extend
time(4)
25
ms
tf
Clock/data fall time
Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15)
20 + 0.1
Cb(5)
300
ns
tr
Clock/data rise time
Fall time tf = 0.9 VDD to (VILmax – 0.15)
20 + 0.1
Cb(5)
300
ns
Cb
Total capacitance of one bus line
400
pF
Figure 5-1. I2C/SMBus/PMBus Timing Diagram
Figure 5-2. Bus Timing in Extended Mode
5.7
Power Supply Sequencing



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