VCNL4100

www.vishay.com

Vishay Semiconductors

Rev. 1.2, 30-Aug-16

4

Document Number: 84319

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

PARAMETER

SYMBOL

STANDARD MODE

FAST MODE

UNIT

MIN.

MAX.

MIN.

MAX.

Clock frequency

10

100

10

400

kHz

Bus free time between start and stop condition

4.7

-

1.3

-

μs

Hold time after (repeated) start condition;



after this period, the first clock is generated

4.0

-

0.6

-

μs

Repeated start condition setup time

4.7

-

0.6

-

μs

Stop condition setup time

4.0

-

0.6

-

μs

Data hold time

3450

-

900

ns

Data setup time

250

-

100

-

ns

4.7

-

1.3

-

μs

4.0

-

0.6

-

μs

Detect clock / data low timeout

25

35

-

-

ms

Clock / data fall time

-

300

-

300

ns

Clock / data rise time

-

1000

-

300

ns

{{

P

Stop Condition

S

Start Condition

{{

P

S

Start

Stop

I

CLOCK

(SCLK)

I

DATA

(SDAT)

I

CLOCK

(SCLK)

I

DATA

(SDAT)